I'm teaching myself about polyphase clock sync for demodulation of OQPSK. An article from gnuradio.org entitled "Polyphase Clock Sync" makes references to a 2nd order loop. The context seems to suggest that loop means phase locked loop. That begs the question, "What is a second order phase locked loop?"
I think that a 2nd order PLL should be the image above, in which an outer loop has had its NCO replaced by a PLL. The idea can be applied N times to make an Nth-order PLL.
However, when I Google, "what is a second order pll", I am quickly confronted by confusing uses of the word, some of them vague or sloppy. Take for example, What is the difference between first order, second order, and third order phase locked loops? from this site. The currently accepted answer starts out with, "It seems to me the accepted answer (by Sparky256) views the PLL simply as a filter and completely ignores its actual purpose..." which sums up most of the other articles I have read about higher order PLLs. Several authors see the word order and start talking about filter order, control system order, the order of everything except the PLL.
I still don't know what a 2nd order PLL is.
To make things worse, diagrams are in short supply. Almost nobody draws a picture when talking about these things.
Here are my questions:
- Is my schematic of a higher order PLL correct? If not, what exactly is this mythical creature known as a high order PLL?
- In the context of recovering clock in a PSK demodulator, is this an appropriate circuit to use? (I realize that for QPSK one would need a complex valued generalization of the circuit above, but how exactly to do that is a separate question.)
Edit: NCO stands for Numerically Controlled Oscillator. Much of PLL literature uses VCO (Voltage Controlled Oscillator) but those are not very common anymore.
LF stands for Loop Filter.
In case it matters, implementation will be in FPGA.
