How to model PCB parasitics

Question

I am working on a buck converter on a PCB. I would like to run some LTSpice simulations to see the impact of the parasitic inductances and resistances of the traces and coupling capacitances.

Is there any where I can find a very rough ballpark model with values for this? It doesn't need to be specific to my layout. Just any good PCB buck converter design that has measured the parasitic so I can see the effect on my design?

Again, I know this is highly subjective based on the layout but if there is a sample buck converter PCB layout somewhere, where someone has measured these, that would be great.

Answer 1

For starters: trace, pin, via, pad, component body, etc. lengths correspond to about 0.5 nH per mm of length. This is basically μ₀ times a geometric constant (typically 0.2-0.5). It's lesser where conductors are wide and low (above the substrate/plane), and greater when narrower and higher.

This is most meaningful when the elements are placed over solid ground plane, which blocks magnetic fields from coupling to other elements. This makes the coupling matrix of the PCB is sparse, and the circuit is easy to model.

PCB layouts can be arbitrarily poor, in which case the geometric constant may be higher (perhaps 0.4-0.8 even), and the coupling matrix is dense; while it's not impossible for such a design to make it through EMC, it's vastly more difficult not just to achieve low emissions (or adequate susceptibility), but to diagnose and improve the system in case it does not. (That is, short of introducing planes and additional filtering anyway -- immure the nasty tangle of wires inside a metal box and heavily filter any wires to it.)

So, keep this in mind for choosing a basic design approach for the layout.

There are simulation tools which can extract the inductance matrix (or s-parameters for RF purposes) of a PCB, but they are fairly pricey, of course.