I'm a VHDL guy for work, so please forgive if this question is dumb.
I asked a buddy to lay out a board for me. The maximum voltage is 2 kV. He said he can't do it because the voltage is too high. (I offered to pay him too so that's not the problem.) However, I don't buy that because:
The highest rated voltage of any component is 650 V, and I never exceed that. Actually, I keep everything lower than roughly 80% of the rated voltage. I'm ganging devices in series, adding 1M resistors across the collector-emitter junction to share voltage evenly, etc.
As long as I keep conductors far enough apart, such that the breakdown voltage between them is more than, say, 10x the potential difference, I don't see how arcing is even possible. Also, I put snubbers across every junction that sees a large voltage difference, so brief spikes should not be possible.
It's trivial to break the design up into smaller boards, so that no individual board has more than 650 V across it. Then I can add an extra cm or whatever between boards to prevent arcing.
So I downloaded KiCad and laid out a few simple boards. Now I'm tackling the design I care about.
My question is how to automate point #2: Is there a way to tell KiCad, "Node 2 has a maximum magnitude of 650 V relative to ground. Node 3 has a maximum magnitude of 50 V relative to ground. So route the traces any way you want, as long as there's 7 kV (= 10 * (650 + 50)) of clearance between nodes 2 and 3"? If so, how does one do this?
