You circuit is overly simple to simulate a voltage-mode (VM) type of buck converter. The feedback path which contains the compensator must be of type 3, meaning 1 pole at dc, 2 zeroes and 2 poles. The crossover frequency must be selected around 3-5 times the resonant frequency of the \$LC\$ network. I recommend you take a look at my APEC 2009 seminar to gain understanding on how to compensate a converter. Failure to do it properly will lead to the instability you have observed.
Rather than using PSIM, I would recommend SIMPLIS which is truly tailored for switching converters design and optimized for ac analysis. You can consider the buck VM template, part of my ready-made templates you can freely download from my page, and the compensation is automated. The cool thing is that most of these examples work on the free demo version:
One common issue with the simple architecture you have proposed is the lack of clamp on the error voltage. If your sawtooth swings from 0 to 2 V for instance, then you have to clamp the error voltage below 2 V unless you want to go to 100% duty ratio. You can do it at the error amp level or via a limiter as I did in the diagram. The low voltage must also be clamped above ground, unless you want to go to 0% duty ratio (skip cycle). I usually clamp between 100 mV and 1.8 V which, for a 2-V peak sawtooth limits the duty ratio between 5-90%.
Your circuitry to control the switch is ok for simulation purposes but, in reality, an integrated circuit implements a latch to avoid the classical double-pulse issue, meaning a glitch can occur on the comparator output during the transition at high current. A D-flip-flop will safely latch the turn-off order and wait for the next clock cycle to restart. Finally, the capacitor you've installed at the (-) pin of the op-amp does not have any effect considering the virtual ground there.
