How to achieve coherent sampling in practice

Question

In the context of measuring a sinusoidal source with an ADC, coherent sampling (i.e. capturing an integer number of periods) allows the use of a rectangular window without spectral leakage.

How does one actually do this in practice?

I am testing a 16 bit ADC that is sampling at 5 MSPS. I set my source to 97.75 Hz to get 41 periods in \$2^{21}\$ samples. Looking at the result, I am missing about 1/8th of a period, and there is spectral leakage. Using a flattop window, the spectral leakage will be at about -95 dB, which is pretty close to where a 16 bit ADC performs. I don't think it would be good enough for something like a 20 bit ADC.

What is a practical bench setup to measure a sine source with an ADC and sample coherently?

Answer 1

You can use a PLL (phase-locked loop) to lock the ADC sampling frequency to the input sine signal.

The bandwidth of the PLL has to be chosen to minimize the overall system's phase jitter and drift - if the input signal changes in frequency quickly, the PLL has to have high bandwidth so it can follow these changes properly, and if the input signal is very stable, the PLL should have low bandwidth to minimize its output jitter.

With a good enough PLL (and zero-crossing detector), you can make the ADC start and stop sampling exactly during the zero-crossing of your waveform while still capturing an exact power of two of samples. The PLL will tune the phase and frequency of the ADC's clock signal accordingly.

When designing your own PLL circuitry to generate an appropriate ADC clock, you might want to consider a multi-stage approach: First a low-frequency PLL that multiplies the signal frequency with a factor of (for example) 256 to get it from the 100Hz range into the 20kHz range, then by another 256 or so to get it into the MHz range. If those multiplication factors are still too large, you could use a three-stage design instead: Three cascaded 64x stages will get you to about 26MHz, which is ideal for many ADCs.

Answer 2

In the context of measuring a sinusoidal source with an ADC, coherent sampling (i.e. capturing an integer number of periods) allows the use of a rectangular window without spectral leakage.

Coherent sampling means that your sampling clock is derived from the same clock as your signal source. The two clocks are said to be coherent because they are phase locked.

I am testing a 16 bit ADC that is sampling at 5 MSPS. I set my source to 97.75 Hz to get 41 periods in $2^{21}$ samples. Looking at the result, I am missing about 1/8th of a cycle, and there is spectral leakage.

That is incoherent sampling since you're using an unrelated 5 MHz clock.

The error of 1/8th of a cycle corresponds to a 0.3 % error in the source or the ADC clock. Is the solution to use frequency sources with better accuracy, or manually tune the frequencies until coherent sampling is achieved?

In coherent sampling the error goes to zero as you observe over long periods since the same clock generates both the signal and sampling clock. Typically this involves a PLL or clock divider. So to generate you 97.75 Hz signal, divide down your 5 MHz clock.

Answer 3

The other two answers at this time refer to using a PLL. I want to say what worked for me, in practice.

I connected the 10 MHz sync output of my clock generator to the sync input of my AP555x audio analyzer which I am using to generate the source signal. Selecting the sync input as the reference clock for the AP555x and setting the input frequency to \$M/N\cdot f_s\$ where M is the number cycles in the input signal (41), N is the number of samples (\$2^{21}\$), and \$f_s\$ is my sampling frequency (5 MHz), I was able to take an FFT of the ADC output using a rectangular window with no spectral leakage.

The input frequency was rounded to 3 or 4 decimal places, but it looks like it still worked.