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Here is the diagram. enter image description here

Here is the strange wave form given by Ib(Q1) enter image description here

The following is the Spice netlist

* G:\document\LTspice\multi_stage.asc
C1 N005 in 1µ
R1 N001 N005 47k
R2 N005 0 10k
R3 N001 N002 4.7k
R4 N006 0 1k
Q1 N002 N005 N006 0 myBJT
Q2 N004 N003 N007 0 myBJT
R5 N003 N001 47k
R6 N003 0 10k
R7 N001 N004 4.7k
R8 N007 0 1k
C2 N006 0 100µ
C3 N003 N002 1µ
C4 N007 0 100µ
C5 N004 out 1µ
V1 in 0 SINE(0 1u 314)
V2 N001 0 10
.model NPN NPN
.model PNP PNP
.lib C:\Users\hello\Documents\LTspiceXVII\lib\cmp\standard.bjt
.tran 0 10 9.995 uic
.model myBJT AKO: BC547B (BF=150)
.meas vmax max V(out)
.meas vmin min V(out)
.meas vpp pp V(out)
.meas V1 PP V(in)
.meas V2 PP V(out)
.meas Gain param V2/V1
.meas I6 pp I(R6)
.meas I5 pp I(R5)
.meas Ix pp I(C3)
.meas Ib2 pp Ib(Q2)
.meas total param I5+I6+Ib2
.meas Ib1 pp Ib(Q1);
.meas Ic1 pp Ic(Q1);
.meas beta param Ic1/Ib1
.backanno
.end

Why do we have the red part at the beginning part the wave in the following picture? enter image description here

I got the following picture when I use .tran 0 10 9.995 1u uic

enter image description here

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  • \$\begingroup\$ It's a simple circuit, maybe use a Vero board and a real oscilloscope? \$\endgroup\$
    – NaturalDemon
    Commented Feb 14, 2023 at 17:39
  • 2
    \$\begingroup\$ Try taking out uic (skip initial operating point solution) in your simulation command \$\endgroup\$
    – GodJihyo
    Commented Feb 14, 2023 at 17:50
  • 2
    \$\begingroup\$ Why can't you set the maximum time step? Also, why do you enable uic? \$\endgroup\$
    – G36
    Commented Feb 14, 2023 at 18:24
  • 1
    \$\begingroup\$ Like others have mentioned, don't use uic. Use startup instead, which is the first checkbox option in the .tran settings window. \$\endgroup\$
    – Ste Kulov
    Commented Feb 14, 2023 at 18:32
  • 2
    \$\begingroup\$ See my answer here: electronics.stackexchange.com/a/652838/254890 \$\endgroup\$
    – Ste Kulov
    Commented Feb 14, 2023 at 18:36

1 Answer 1

Reset to default
4
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This has something to do with the integration method. Trapezoidal and modified Trapezoidal will give the odd glitch when uic or startup are used in the .tran card.
If you use Gear integration method, the circuit behaves as you expect. Select the integration method in Tools -> Control Panel -> SPICE.

As stated in the comments below the original question:

  1. Removing the uic or startup condition solves the issue.
  2. Making the time step smaller in the .tran card is helpful. 100us helps, but not quite perfect; 10us looks pretty good.

Good practice with SPICE, do not leave floating nodes in SPICE as you have done with C5.

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1
  • 1
    \$\begingroup\$ I recommend against setting the integration method to Gear within the control panel since that setting persists (denoted by the asterisk) until you change it back, and Gear generally causes more problems than Modified Trap. For problematic schematics which require Gear, I suggest adding a .options method=gear SPICE directive to the particular schematic in question to force the change only on that schematic. \$\endgroup\$
    – Ste Kulov
    Commented Feb 17, 2023 at 12:16

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