Why do 74-series counters label their enable pins T and P?

Question

A few 74-series counter ICs I’ve looked at have two enable pins, and they’re labeled “T” and “P” (for example, the 74LS161A, or 74ALS867A). The “T” input affects the ripple carry out, and the data sheets say this pins are used to enable cascading ICs, but they’re not precise about how to connect them.

After some experimentation, I tied the ENT pins together to use as a global enable, and tied the RCO of the lower stage to the ENP input of the upper stage:

This behaves as expected, but what do “T” and “P” stand for?

Update: Spehro’s answer gives the names for P & T, but I’m also looking for an explanation of why the subtle difference in internal handling of the two signals is useful, since both must be asserted to count. ErikR’s answer references a video that discusses the carry out propagation delay, and there might be some insight there, but I didn’t quite get it on first viewing.

Answer 1

To expand on Spehro's answer, P and T are the parallel and trickle enables for use in multi-stage counters. P enables all the counters in parallel. T is like a ripple carry, that "trickles" from counter to counter.

The reason to do this is to improve performance. The slow, easy approach is to use only the T enable. In this case, each chip needs to receive a carry out from the previous chip before it can generate its carry. So with N chips, the worst case is that you need to wait N delays for all the chips to count.

The other approach is to use the P enables as well. The circuit is wired so the T carry signals are generated in advance, so they can ripple through while the circuit is idle. When you clock the counter, if the first counter has a carry, it enables P and all the other chips count in parallel, so you delay is roughly 2 units instead of N.

In other words, the counter chips after the first one assume that they will get a carry and produce carries as needed, but they don't actually change the count. They wait until the first chip produces a carry and enables the other chips in parallel through the P pin. Since they're ready, boom, they can update the count immediately.

I traced this usage back to the 1973 Fairchild TTL Applications Handbook, so the parallel and trickle names aren't backronyms. To quote the datasheet, "As the second stage advances to its terminal count, an enable is allowed to trickle down to the last counter stage, but has the full cycle time of the first counter to reach it."

Answer 2

This answer refers to CET and CEP pins as "Count Enable Toggle" and "Count Enable Pulse", with reference to some unseen paper documents (older than my TTL databook, it seems).

This TI datasheet refers to Parallel and Trickle, but appears to me much newer so possibly a backronym.

In any case, from here is the proper way to use the inputs to make a synchronous counter:

Note that, unlike a ripple counter, all the counters are clocked simultaneously.

Answer 3

Here's a schematic from a typical 'ls161 counter, that shows the internal connections for the enable P and enable T inputs. The circled signal on the right is the ripple carry output.

Diagram is from the AMD Schottky and Low-Power Schottky Data Book, Second Edition from 1977. Yes, it is a bit worn around the edges.

Answer 4

This video might explain it:

Cascading of Synchronous Counters

https://www.youtube.com/watch?v=4OuwZlqZdF8

At 1:31 there is this example of how to cascade three synchronous counters:

The RCO of the first counter goes to the ENT of the second, but the RCO of the second counter goes to ENP of the third.

At 2:20 the scheme for cascading four counters is shown:

The video also discusses the timing considerations that you need to pay attention to in order to maintain synchronous operation and this is primarily the carry signal delay vs. clock period.

As for why "T" and "P" were chosen, I'm pretty sure "P" stands for "propagation" as in "carry propagation".