Why would you sense peak inductor current at the high-side PMOS transistor rather than at the NMOS?

Question

I found this image for peak current mode sensing here.

Is there any reason that you sense the peak inductor current from the MP instead of theMN transistor? I know that ideally both should work but I wonder if there is something relating to practice that sensing MP is prefered.

This is an example from the site:

Please tell me what is wrong with my understanding.

Vc is controlled by the load condition. In heavy load condition, Vc increases which in turn increases the duty cycle and inductor current. Conversely for light load condition.

The duty cycle is controlled by the peak inductor current. The peak of the inductor current = peak of rising inductor current = peak of falling inductor current. So as long as you can sense the peak, either peak of rising or falling, both should work.

I agree that there are some problems of low-side sensing because of ringing. Is there another reason that makes low-side sensing not work?

How about if we just sense the inductor current instead of high-side or low-side sensing?

Added question related to simulation:

In this simulation you can see that both rising and falling inductor current share the same peak. So would it work with just the falling section of the current?

Answer 1

Because during the cycle when PFET is on, current of PFET and inductor is increasing, and the NFET current is zero.

PFET must be turned off when peak current limit is reached, to terminate the inductor charging cycle.

Answer 2

Since the control circuit is shown, the answer can be discovered by following the logic.

If current never reaches peak, then NMOS never turns off, and the output explodes. Well, maybe not that severe, but at best it reduces to a voltage-mode control (Iramp controlled only, Isense = 0). And then compensation and startup/fault response sucks.

You could invert the current sense and ramp, and swap the flip-flop inputs, so it goes high starting from when the low side current drops below threshold, until the next oscillator pulse. But then you lose the peak current sensing feature: it's safer to assume nothing bad will happen during the low phase (it's just circulating load current), less safe to assume the input side always delivers the same slug of charge per pulse. And if the state ever gets stuck high for multiple clock cycles, the output current is completely unknown.

A low-side-sensing control is possible, and indeed typical, when a more complicated solution is employed: e.g. reconstructing high-side current from the low-side current measured during the previous cycle, give or take measurements of, or assumptions about, Vin, Vout, L, etc.; or when constant-on-time control is used (in which case the ΔI is nominally fixed per cycle). The latter forces a low-side half-cycle, and thus current sensing opportunity, periodically; even if the rise in current is unexpectedly high during one cycle, it can just stay low for longer until back within nominal range.

Answer 3

When the hi-side MOS (PMOS) is on the current flows from voltage source (input) to inductor, output capacitor, and load. And energy builds up in the inductor's magnetic field during this time. When the charging current reaches to its peak then the PMOS turns off. And, depending on the driver design and conditions, low-side MOS (NMOS) turns on (it may stay off because its body diode will be in conduction) and initiates the discharge (reset) cycle of the inductor (During the reset cycle the inductor current flow direction won't change, but the voltage across it will reverse therefore the inductor will be reset).

Now, there are few disadvantages of measuring the peak current from NMOS's source:

• Most importantly, the peak of the charging current cannot be detected because PMOS should be turned off once the peak is reached. By measuring the voltage at the PMOS-inductor junction and time-delta will give an idea but it's difficult to implement this at hardware level. So the inductor's saturation may not be prevented. This is useful especially when the output is shorted: The control loop will force the PMOS stay on indefinitely to increase the output voltage, so the inductor current can ramp up to infinity if not interrupted. This will eventually lead to core saturation. High-side measurement will bring an inherent protection for this. It's impossible to detect this with low-side measurement.
• Since there's going to be some time from turning off the PMOS to turning on the NMOS (as stated before, NMOS doesn't have to be turned on but let's assume for a moment that it's going to be), the measured peak current won't be the actual peak current because the inductor will start to discharge. So the real peak current info will be lost (slightly).
• Although the voltage developed across the sense resistor will be ground-referenced which makes the measurement easier by eliminating the use of differential amplifier for the high-side measurement, the polarity will be reversed because the current will flow from source to drain. This brings a negative supply voltage requirement or an extra inverter.