The following uses 3 TTL 74SLS76N J-K flip-flops, which are active low:
However, I'm trying to figure out what the settings for the PR and CLR inputs would be using CMOS CD4027 J-K flip-flops. For example, would the PR and CLR inputs be the inverse of the ones shown above for the number 2 using CMOS: 01 10 01?