In the below current limiter circuit, why is the MOSFET current rising slowly?
Shouldn't the MOSFET current follow the equation \$i_D=\kappa(V_{GS}-V_{th})^2\$?
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asked Oct 7, 2022 at 6:46
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\$\begingroup\$ I assume miller plateau because your pull up impedance (R40+42) is very high. \$\endgroup\$– tobaltCommented Oct 7, 2022 at 7:04
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\$\begingroup\$ Not sure how is it related to Miller plateau since VGS is always constant and not really turning OFF MOSFET \$\endgroup\$– Dynamic_equilibriumCommented Oct 7, 2022 at 8:00
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2\$\begingroup\$ You have to contribute Miller charge, when VDS is changing (while VGS is constant) \$\endgroup\$– tobaltCommented Oct 7, 2022 at 8:53
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\$\begingroup\$ Can you add values for R46 and R38? I've worked with circuits that are very similar to this and they typically have a slow start slew rate that is intrinsic to them. \$\endgroup\$– cEEaCommented Oct 7, 2022 at 14:00
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1\$\begingroup\$ C31 adds even more capacitance to make the effect more pronounced..But even without it, the gate capacitance must be charged if you want the FET to saturate at higher current. \$\endgroup\$– tobaltCommented Oct 8, 2022 at 18:04
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1 Answer
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- Because the MOSFET probably isn't doing what you think it is doing.
If the "current limiting circuit" is doing what it is supposed to and isn't active, think about what you have. You effectively short the MOSFET drain to the gate. This is called being "diode connected" and the MOSFET becomes a resistor with a value of 1/gm. That's acting in the "linear" region until your "current limiter" kicks in (which seems to be exactly what is happening--the transistor kicks on, current rises linearly with voltage, and then the limiter kicks in and prevents further current increase).
- If you are trying to do active current limiting, MOSFETs aren't necessarily the best choice.
MOSFET's have very high gain from gate to current (square term) which makes control and stability problematic. You likely would be better off using some form of BJT in saturation where Ib * beta = Ic. Notice that the output is linear with respect to the input rather than exponential.
- "Fuzziness" on a SPICE simulation is rarely a good thing--especially fuzziness that disappears and reappears.
Fuzziness means the simulation isn't stable and may not be giving you valid results. This could be a convergence problem in SPICE itself (it looks like you are using LTSpice which is tuned for switching circuitry rather than general simulation). It could also be a real stability problem in your circuit.
Good luck.
answered Oct 7, 2022 at 23:25
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\$\begingroup\$ Regarding item 3: I have edited the snap without the fuzziness \$\endgroup\$ Commented Oct 8, 2022 at 2:35