If I read that a line has a limit of 1 TTL LS load, does it mean that I can attach only a TTL gate? I know that other options exist, for example, the HC, however, in the case I have only LS gates, how many of them can attach to the line?
Does "1 TTL LS load" refer to a single TTL LS gate? If it looks like a silly question: sorry I'm a newbie.
Compared with modern CMOS logic, TTL was rather power-hungry. That's still true, to a lesser extent, with the later LS TTL. Newer ICs may struggle to drive the logic inputs of older TTL devices.
So the "limit of 1 TTL LS load" means that your line can drive an LS TTL load, but only one of them. One TTL LS Load means one input of one logic gate.
If you need more than that, use an LS TTL buffer, which has one input but can power several other logic inputs (check the data sheet).
74LS TTL input spec is basically the safe Vin(low) or Vil voltage with a 20k Pullup thru a diode.
The 74HCxx family can certainly drive a lot more than 1 and possibly 10 LS04 TTL loads low "0".
Where did you read this? In any case, here is how you prove it. I expect it was for CD4xxx old CMOS rated for 18V which had 300 to 3k output impedance due to Vdd.
The LS04 spec like most 74LS chips for Vil (input low) is 0.4V/0.4mA = 1kohm equivalent resistor to pull down the input to this logic "0" voltage.
The 74HC04 spec like most CMOS at 25'C or less is 0.26V / 4 mA = 65 Ohms
The open circuit for TTL is actually a logic "1" with very poor noise immunity and that is at 1.2V or two Vbe drops. +/-0.1
Using Norton equivalent, how many 74LSxx TTL can you drive with a 74HCxx at 5V minus 10% tolerance
Use the 74LS input specs 0.4 mA @ 0.4V and 74HC specs of 65 Ohms RdsOn equivalent across the Nch output active low.
The worst case TTL input low current is basically the worst case poly-resistor value of 20k nominal lowing to 10k. 74HC CMOS can easily drive that below 0.4V
proof by sim using Schottky diodes and hFE =30
Not many designers will know or remember this, so let me tell everyone where TTL load power goes. A 20k input 74LS resistor has a wide tolerance and if it is 10k you will get the exact Vil, Iin specs and this is confirmed in my simulation.
Unlikely anyone would choose to use an actual LSTTL gate today. An LSTTL output driving a single load must source 20uA with a minimum voltage of 2.7V and sink 400uA with a maximum voltage of 400mV to have full noise immunity.
If the output actually swings from 0 to Vdd then it can drive virtually unlimited CMOS inputs however the speed may be unacceptably slow with a heavy capacitive load. Typically you'd have another spec that lists test load capacitance and CMOS-applicable voltage levels. Alternatively, the HCT family has TTL input levels, but it's best to avoid using that family if possible.
The Vih for an HC gate is typically 3.15V so the 2.7V spec not only does not guarantee noise margin it does not guarantee functionality. So look to another line in the datasheet.
