2
\$\begingroup\$

Given the image below, what would be the best place to place the PHY and Magnetics, (connectors can move)?

I appreciate that Ethernet best design practices are not being followed here, but given this scenario how I can I maximise chances of successful ethernet comms?

Key Points:

  • Connectors can move (wire to board is not RJ45)
  • Space constrained by outers all around PCBs
  • Centre board intended as isolation between top and bottom board (Isolate power supplies and digital isolation etc for comms, level shifters etc)
  • Boards 150x150mm
  • Ethernet 10/100 Base-t
  • Wire to board connector does not include magnetics

PCB stack with ethernet entering in the wire to board connector on top board:

PCB stack with ethernet entering in the wire to board connector on top board

\$\endgroup\$
3
  • 2
    \$\begingroup\$ It depeds if the board is 10 cm or 1 meter wide and how much board to board connectors deteriorate the signal. You also don't say if this is a magjack. Nor if this is your typical household Gigabit or Fast Ethernet or something more exotic. \$\endgroup\$
    – Justme
    Commented Aug 22, 2022 at 17:06
  • \$\begingroup\$ @Justme Thanks for the comment, I have since added the board dimensions, will add the ethernet. Its not a magjack, I thought alluding to the fact that the wire to board connector wasn't RJ45 and that I need advice on placing magnetics that would have ruled out Magjack connector. Ethernet is 100 Base-T I'll update Q \$\endgroup\$
    – Pop24
    Commented Aug 22, 2022 at 17:22
  • \$\begingroup\$ Can grounding be provided by the sides / support blocks things? Or is there an enclosure? What kind of EMC exposure will this have (for both emissions and immunity purposes)? \$\endgroup\$
    – Tim Williams
    Commented Aug 23, 2022 at 6:54

3 Answers 3

Reset to default
1
\$\begingroup\$

Considering the Ethernet traces are a source of noise (long cable) I'd place the magnetics close to the connector. From there the remaining placement doesn't really matter that much as long as you pay attention to the impedance discontinuances across the connectors and traces.

I'd also place the PHY close to the magnetics because it will usually be easier for routing the traces since you have your normal signal ground as reference.

\$\endgroup\$
2
  • \$\begingroup\$ Thanks for taking the time to answer much appreciated, will wait a few days to see what other comments come about, but seems sensible thanks for the explanation. \$\endgroup\$
    – Pop24
    Commented Aug 22, 2022 at 17:23
  • \$\begingroup\$ The problem then is, if PHY is near magnetics and connector, you need to route the 25 MHz MII or 50 MHz RMII bus from PHY to processor through a long route and connectors. So it depends on the connectors and PCB routing and how many layers the PCB has which option makes more sense in this case, but in general, you are correct that Ethernet connector, magnetics and PHY should be quite close together, maybe max 2 inch between them says some appnotes. \$\endgroup\$
    – Justme
    Commented Aug 23, 2022 at 7:37
0
\$\begingroup\$

You should expect high voltage transients from the wire, so you need to have a large isolation gap from the tracks to other elements on you PCB and therefore taking a lot of space.

Placing the processor is usually a tradeoff between two buses (Ethernet and USB/SPI/etc) on the opposite sides, one as an input, the other as output. If the input is from a cable, then it might make sense to minimize the feeding end, as you will have control on signal integrity within your board, but not on the feeding signal. The feeding input also needs to withstand ESD, so keeping the tracks short makes sense. If your processor is generating the data or the same ethernet port is the feeding port, then it makes sense to keep the high speed routings to a minimum and not passing any connectors.

\$\endgroup\$
6
  • \$\begingroup\$ Ethernet is a transformer coupled isolated interface. The cabling side must not have ESD protection or any other DC reference to any ground of the device. And this is more a trade-off if the MII side or MDI side of Ethernet PHY should be longer and that's not simple to decide. \$\endgroup\$
    – Justme
    Commented Aug 23, 2022 at 4:06
  • \$\begingroup\$ Edited to leave out the possibility to not have the cabling side isolated. \$\endgroup\$
    – Ralph
    Commented Aug 23, 2022 at 5:18
  • \$\begingroup\$ @Justme Transformers rated for unclamped ESD are a rare sight indeed; even medical grade 6kV isolation is rare, and ESD is easily still more than that. Traditionally, ESD protection is afforded by a 1.5nF capacitor to ground, wherever that ground might happen to be: if not onboard (ground plane), then hopefully a metal enclosure or something. \$\endgroup\$
    – Tim Williams
    Commented Aug 23, 2022 at 6:52
  • \$\begingroup\$ @TimWilliams Ethernet connector chassis can and may be connected to device chassis and it may be device signal ground as well. But like I said, the data pairs don't have DC connection to anywhere, they are AC terminated. If you want ESD protection, the wire side has ESD diodes between pairs, and the PHY side can have standard ESD diodes to ground. But data pairs can still sit at any DC voltage in referece to device ground or each other, e.g. due to PoE. \$\endgroup\$
    – Justme
    Commented Aug 23, 2022 at 7:01
  • \$\begingroup\$ @Justme Right. I read "ESD protection" as including any mitigation practices: and the shunt capacitor is for this purpose explicitly. I see your meaning is more restricted, i.e. semiconductor devices (and maybe GDTs or spark gaps?), and so the capacitor seems to be ignored, or an oversight. I just wanted to point out for readers that there are multiple approaches here, and we should be careful which ones we mean. \$\endgroup\$
    – Tim Williams
    Commented Aug 23, 2022 at 7:09
0
\$\begingroup\$

Depends, if you are using MII (17 conductors plus extra optional signals), then it runs at 25MHz. 25MHz would be easy to maintain signal integrity as a wavelength is over 1meter and through connectors with capacitance. The phy could potentially be placed on the upperboard next to the connector.

The downside to using MII is you need extra pins on the connectors, which may not be good for your design. a comprise might be to put the PHY on the middle board with RMII which runs at 50MHz and uses less conductors (at least 9).

If you did put the PHY on the middle board matching the diff pairs becomes more problematic and you'd also have to send the signals through a connector. Sending the diff pairs to the bottom board may prove problematic.

\$\endgroup\$

Not the answer you're looking for? Browse other questions tagged or ask your own question.