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I have a board (DUT = device under test), featuring (in addition to other things, which are not important for this question) 2 connectors - A and B. The connectors are connected 1:1 at the DUT.

 +--------------+  
 |      DUT     |
-|A1----------B1|-
-|A2----------B2|-
-|A3----------B3|-
-|A4----------B4|-
-|A5----------B5|-
 |              |
 +--------------+  

I need to test, that the signal path of these two connectors are not open and ideally as a bonus, also they are not shorted. My intention is to use a GPIO board, which I have an experience with.

Test approach for first 2 pins of each connector:

loopback    +-----------+     GPIO board          
       |----|A1| DUT |B1|---- O                   
       |----|A2|     |B2|---- I                  
            +-----------+                        
  1. A1 and A2 pins are shortened using a hardware loopback
  2. B1 pin is set to output at the GPIO board, pin B2 to input
  3. The output pin is set to H and then to L accordingly. The same states are expected to be read at the input pin.

Test approach for the latter 3 pins of each connector:

As the total number of the pins is not even, the remaining odd number of pins would be shortened and tested together:

loopback    +-----------+     GPIO board          
       |----|A3| DUT |B3|---- O                   
       |----|A4|     |B4|---- I                  
       |----|A5|     |B5|---- I                  
            +-----------+                        
  1. A3, A4 and A5 pins are shorted together with a hardware loopback
  2. B3 pin is set to output at the GPIO board, pins B4 and B5 to input
  3. The test step would be similar to the previous state with 2 pins, just two outputs will be read at once.

My questions are:

  1. This approach will test, if there are any opens in the DUT signal paths. Is this approach robust enough to test any potential opens?
  2. This approach will not test any potential shorts. Is there any additional easy approach to test for the shorts also?
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  • \$\begingroup\$ Do you want to find all shorts or only adjacent? \$\endgroup\$
    – Jens
    Commented Jul 1, 2022 at 18:07
  • 1
    \$\begingroup\$ Could you use an ADC to measure a voltage between B pins? The you could put a resistor across the loop back and measure that you get an expected voltage across the loopback. \$\endgroup\$ Commented Jul 1, 2022 at 21:52
  • \$\begingroup\$ Adjacent shorts would be sufficient. \$\endgroup\$
    – ethcz
    Commented Jul 2, 2022 at 0:08
  • \$\begingroup\$ user1937198, thanks, but can you be more specific? ADC can be used, but I don't have much ADC inputs. maybe only one. Also, I cannot switch different loopbacks or resistors during the test. The goal is to connect "something" to connector A, "something" to connector B, execute the test and then disconnect both "something". Also, the number of 1:1 signals at the DUT might be more than 5, I just wanted to show the principle, that even signals will be tested in pairs and if there is an odd remainder, they will be tested in a group of three. \$\endgroup\$
    – ethcz
    Commented Jul 2, 2022 at 0:17

1 Answer 1

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If you want to verify no wires are open and no wires are shorted but not verify that the end-to-end wiring is correct (for example, pin 1 on one end is not connected to pin 2 on the other end instead), you could do a two-step approach.

Test 1 is done with the far end disconnected. Run through each line, setting that line high and verifying that all other lines input low. This tests for shorts.

Test 2 is done by shorting together the far end pins, as you specified. Here, it is sufficient to set one line high and verify that all other lines read high.

To avoid noise, all inputs must have pull-down resistors, but not so large small a value that all put in parallel won't overload the output.

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  • \$\begingroup\$ This is the solution I was looking for, thank you! By pull downs, do you mean to avoid noise in case of bad path at the DUT, so a fail positive result is avoided? And by ”not so large”, don't you mean "not too small resistance value" instead? \$\endgroup\$
    – ethcz
    Commented Jul 2, 2022 at 14:25
  • \$\begingroup\$ Also you are right, verifying, if the end-to-end wiring is correct is not necessary. The DUT is a PCB, not cable, so the wiring cannot be wrong. \$\endgroup\$
    – ethcz
    Commented Jul 2, 2022 at 14:31
  • \$\begingroup\$ @ethcz You are correct. I have corrected the typo. \$\endgroup\$
    – DoxyLover
    Commented Jul 3, 2022 at 5:18
  • \$\begingroup\$ Great, thank you for your insights! \$\endgroup\$
    – ethcz
    Commented Jul 3, 2022 at 18:18

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