I have a board (DUT = device under test), featuring (in addition to other things, which are not important for this question) 2 connectors - A and B. The connectors are connected 1:1 at the DUT.
+--------------+
| DUT |
-|A1----------B1|-
-|A2----------B2|-
-|A3----------B3|-
-|A4----------B4|-
-|A5----------B5|-
| |
+--------------+
I need to test, that the signal path of these two connectors are not open and ideally as a bonus, also they are not shorted. My intention is to use a GPIO board, which I have an experience with.
Test approach for first 2 pins of each connector:
loopback +-----------+ GPIO board
|----|A1| DUT |B1|---- O
|----|A2| |B2|---- I
+-----------+
- A1 and A2 pins are shortened using a hardware loopback
- B1 pin is set to output at the GPIO board, pin B2 to input
- The output pin is set to H and then to L accordingly. The same states are expected to be read at the input pin.
Test approach for the latter 3 pins of each connector:
As the total number of the pins is not even, the remaining odd number of pins would be shortened and tested together:
loopback +-----------+ GPIO board
|----|A3| DUT |B3|---- O
|----|A4| |B4|---- I
|----|A5| |B5|---- I
+-----------+
- A3, A4 and A5 pins are shorted together with a hardware loopback
- B3 pin is set to output at the GPIO board, pins B4 and B5 to input
- The test step would be similar to the previous state with 2 pins, just two outputs will be read at once.
My questions are:
- This approach will test, if there are any opens in the DUT signal paths. Is this approach robust enough to test any potential opens?
- This approach will not test any potential shorts. Is there any additional easy approach to test for the shorts also?