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4bit ripple carry adder

I denote delay timing as "@ value". As you can see the picture above, C_in0(carry in 0), A0(input A's 0th bit), and B0 are initially ready so there is no delay which means they all have @0 delay. The rest of delays is also indicated on the picture.

My Question is why S0 is @2 not @1. To my knowledge, the sum part in Full Adder has 2 levels that are xor both. Therefore if an incoming Cin's delay is n, the total delay of the part is n+1. For example, if you look at FA2 in the above picture you can see Cin1 is @2 so S1's delay is 3(2+1).In my example, Cin0 = 0 so the S0's delay should be 1. Maybe the picture below helps you understand what I am saying. The sum part in Full adder

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  • \$\begingroup\$ And what when the incoming A's delay is n? Then what is the total delay of the part? \$\endgroup\$ Commented Jun 3, 2022 at 10:01
  • \$\begingroup\$ Thank you for your comment. Let me be clear, If Cin's delay is n, and A and B's delay is 0 the total delay for the sum part in full gate is n+1. \$\endgroup\$ Commented Jun 3, 2022 at 10:30
  • \$\begingroup\$ what if n is less than 0? if A's delay is 0 and B's delay is 0 and Cin's delay is -3 does that mean the sum's delay is -2? No. Why not? \$\endgroup\$ Commented Jun 3, 2022 at 10:35
  • \$\begingroup\$ Oh I've never thought that delay can has minus value. Anyway thank you for your comment. First of all, I am considering the worst case only here for your information. As you can see the second picture, inputs have no delay. I think it is obvious because inputs are always ready to get into the gate. On the other hand carry_in is not ready because delay has been rippled through the carry propagation. So if C_in has @n delay, at the first xor gate, it takes @1 and then it takes n+1 at the second xor gate. \$\endgroup\$ Commented Jun 3, 2022 at 10:46
  • \$\begingroup\$ @SeungHwanKwan I'm not sure what you mean but I think you are still ignoring A and B. Start thinking about A and B. If C_in's delay is 100 and A's delay is 200 and B's delay is 300 then what is S's delay? Is it 101? Or is it not 101? \$\endgroup\$ Commented Jun 3, 2022 at 10:49

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