2
\$\begingroup\$

I'm using the IRF7422 (P Mosfet - warning opens a *.pdf) FETKY and I'm experiencing a strange issue.

I am pulling the gate high to +5V which should theoretically cause the source-drain channel to stop conducting. However, if I subsequently measure the voltage present at the source I get 4.5 V. It seems whatever voltage is present at the drain node is fed back to the source with a 0.5V drop. Is this to be expected? There is nothing else connected to the source node.

enter image description here

\$\endgroup\$
4
  • \$\begingroup\$ Since the schottky diode is 0.5 V that might be a big hint that you have a wiring error. A schematic of your test setup would be helpful. \$\endgroup\$
    – placeholder
    Commented Mar 24, 2013 at 16:01
  • \$\begingroup\$ Schematic: i.imgur.com/w8RDpvC.png \$\endgroup\$
    – Vanush Vee
    Commented Mar 24, 2013 at 23:06
  • 1
    \$\begingroup\$ I edited the URL to the datasheet to go directly to the item, rather than through Google's labyrinth. URL's should be "star grounded" to avoid picking up noise. :) \$\endgroup\$
    – Kaz
    Commented Apr 24, 2013 at 1:29
  • \$\begingroup\$ Aaaaagh! For the love of the flying spaghetti monster, please draw your schematic with the freaking FET schematic symbol! The whole point of a schematic is to show the functional representation of a circuit, and let the computer map that to the physical pins. Drawing your schematic FETs like the physical pins on the package is stupid. \$\endgroup\$
    – Connor Wolf
    Commented May 24, 2013 at 7:45

2 Answers 2

Reset to default
4
\$\begingroup\$

You simply have the FET wired backwards, the S & D must be reversed. For a PMOS fet the Source is high and the Drain is low. You have the drain connected to Vcc.

\$\endgroup\$
2
\$\begingroup\$

This is expected behaviour: Every MOSFET has a so called Body diode. It is shown in the schematic on page 1 of your data sheet: The diode between D and S in the FETs circle.

N-Channel FET has this diode too, with polarity reversed.

\$\endgroup\$
2
  • \$\begingroup\$ Does that mean that my approach would not work? Schematic: i.imgur.com/w8RDpvC.png When USB power is not present, gate is pulled low allowing the source-drain to conduct and VBAT provides VCC. Schottky from drain to gate stops VCC pulling the gate high. When USB is present, gate gets pulled high and USB provides VCC and the source-drain closes. But if the drain-source is conducting through the body diode, then my VBAT net is not non-zero and components on the board which should not have power do ! (This circuit was taken from electronics.stackexchange.com/a/36938/18133) \$\endgroup\$
    – Vanush Vee
    Commented Mar 24, 2013 at 23:00
  • \$\begingroup\$ Try a dual P channel Mosfet like FDC6505P. Or add another diode to block the backflow intomthe Mosfet. You don't want to charge your batter like this anyway. \$\endgroup\$
    – Carl Gilbert
    Commented Mar 26, 2020 at 23:31

Not the answer you're looking for? Browse other questions tagged or ask your own question.