Error " Too few nodes: draw " for my simulation High-side driver VN820PT-E

Question

I get a model error in LTspice from adding a high-side driver, VN820PT-E for my library.

But after simulation, I have an error message. " Too few nodes: draw " .

I don't understand this error. Any advice?

Here is the schematic.

This is file.LIB

EESchema-LIBRARY Version 2.3
#encoding utf-8
#SamacSys ECAD Model VN820PT-E
#/14707361/538787/2.49/5/0/Integrated Circuit




* connections:      IN
*                   |   VCC
*                   |   |   OUT
*                   |   |   |   STATUS
*                   |   |   |   |   GND
*                   |   |   |   |   |
*                   |   |   |   |   |
.SUBCKT VN820PT-E   1   2   3   4   5



F0 "IC" 1050 300 50 H V L CNN
F1 "VN820PT-E" 1050 200 50 H V L CNN
F2 "SOT455P1410X1350-5N" 1050 100 50 H I L CNN
F3 "https://componentsearchengine.com/Datasheets/2/VN820PT-E.pdf" 1050 0 50 H I L CNN
F4 "Gate Drivers 9A 36V HIGH SIDE" 1050 -100 50 H I L CNN "Description"
F5 "13.5" 1050 -200 50 H I L CNN "Height"
F6 "STMicroelectronics" 1050 -300 50 H I L CNN "Manufacturer_Name"
F7 "VN820PT-E" 1050 -400 50 H I L CNN "Manufacturer_Part_Number"
F8 "" 1050 -500 50 H I L CNN "Mouser Part Number"
F9 "" 1050 -600 50 H I L CNN "Mouser Price/Stock"
F10 "" 1050 -700 50 H I L CNN "Arrow Part Number"
F11 "" 1050 -800 50 H I L CNN "Arrow Price/Stock"
DRAW
X IN 1 0 0 200 R 50 50 0 0 I
X VCC 2 0 -100 200 R 50 50 0 0 W
X OUT 3 0 -200 200 R 50 50 0 0 O
X STATUS 4 0 -300 200 R 50 50 0 0 P
X GND 5 1200 0 200 L 50 50 0 0 W
P 5 0 1 6 200 100 1000 100 1000 -400 200 -400 200 100 N
ENDDRAW
ENDDEF
#
#End Library

---

Answer 1

Two issues:

• LTspice simulation must include the operation ".lib /path/to/file.LIB" for the .lib file to be loaded (this is not visible in the image.)
• The "file.LIB" appears to be a KiCAD EESchema file type, not a SPICE 3f5 file type. While the format looks similar, SPICE is not going to understand this EESchema file; it is not a SPICE model.

You need a SPICE simulation model, sometimes called a "card" or "deck" file. The contents of this file should look something like the following:

*** SUBCIRCUIT DEFINITIONS
.SUBCKT NAND 1 2 3 4
* NODES: INPUT(2), OUTPUT, VCC
Q1 9 5 1 QMOD
D1CLAMP 0 1 DMOD
Q2 9 5 2 QMOD
D2CLAMP 0 2 DMOD
RB 4 5 4K
R1 4 6 1.6K
Q3 6 9 8 QMOD
R2 8 0 1K
RC 4 7 130
Q4 7 6 10 QMOD
DVBEDROP 10 3 DMOD
Q5 3 8 0 QMOD
.ENDS NAND

The above is taken from the SPICE Page at Berkeley.

Checking ST.com, they don't seem to offer a SPICE model for this item. Web search reveals nothing else. If you can find a SPICE model for this part, it might work, but finding one seems unlikely.