Average current mode control vs peak current mode control

Question

I am reading an application note "Average Current mode control" of switching power supplies written by Lloyd Dixon. Here is the abstract :

Unitrode AN Average Current Mode Control of Switching Power Supplies by Lloyd Dixon

Current mode control as usually implemented in switching power supplies actually senses and controls peak inductor current. This gives rise to many serious problems, including poor noise immunity, a need for slope compensation, and peak-to-average current errors which the inherently low current loop gain cannot correct.
Average current mode control eliminates these problems and may be used effectively to control currents other than inductor current, allowing a much broader range of topological application.

If the average current mode control is better than peak current control why there is still components which are based on peak current control ?

(On several applications I have a problem of noise immunity. Sometimes when I generate a high electric field next to my application, I see that the PWM of the UC384X is stopped as if there was a peak on the ISNS pin...)

Answer 1

It's harder to implement cycle-by-cycle current limiting in average current mode.

Also:

With average current mode control you have the problem of sensing the current. You have to have a sense resistor or network across your inductor and extra circuitry, leading to higher cost and complexity.

With peak current control a simple sense resistor at the bottom of the switch (for buck) can feed directly into the current sense amplifier, so it's easier and cheaper. You do have to implement slope compensation, but that's easily done. Noise issues due to low duty cycle can be mitigated with valley mode control.

Answer 2

ON Semi has elected to obsolete this p/n with better designs.

The advantage of this design is limit the slew rate of charging up current where PWM increases current with voltage feedback as the error becomes smaller with a 1V limit on resetting the SR latch for current sensing.

Yet this also makes it more sensitive to load induced kickback or BEMF when the load steps off from a reactive load and thus might increase the duration of current ramp to cutoff in the opposite direction of what you need for a step down reactive load. I.e. slope compensation.

Instability can occur with integration when the stored energy in the inductor greatly exceeds the demand load causing a need for phase lead compensation (the D in PID control)

As far as your e-field EMI, be sure it is not BEMF conduction noise or else your cables and supply are not well ground shielded. Define your interference induced by radiation or conduction by experiment and report the actual issues that may be causing OCP or OVP shut off on the Is input.

• it could be a design issue from what I tried to explain above, in which case you need more decoupling of the load from the regulated output by of several methods; CM choke, load flyback snubber, RLC damped series load, shielded twisted pairs to load & EMI shielding.

Current and voltage sensing are critical feedback loops that must be tailored to your dynamic load range and acceptable steady ripple voltage. Normally 50% steps are expected but greater steps or driving a nonlinear secondary SMPS can cause issues that demand details, which sometimes maybe be fixed by ultra low small ESR output caps near load.

Answer 3

The question "If the average current mode control is better than peak current control why there is still components which are based on peak current control?" is based on Lloyd Dixon's opinion. In my experience, average CMC is not better than peak CMC. Dixon stated "serious problems" and "poor noise immunity". I have designed scores of power converters using peak current mode for aerospace, both for aircraft and satellites and I NEVER had "serious problems" and "poor noise immunity". Maybe his breadboards were hooked up with huge loops with parasitic inductances. Just guessing but, I don't know why he would conclude something which many power electronics engineers have never seen. Also, his statement that there are peak-to-average current errors that a low current loop gain cannot correct is not true. If you arrange your error signal and slope compensation correctly, you do not end up with this peak vs average error in the first place.