CAN bus expander circuit

Question

I am trying to design a CAN bus expander. In this case I could implement star topology of multiple buses in parallel. It would avoid having problems with reflections and delay.

For this purpose I prepared a simple schematics, that basically reflects RX signal from the CAN transceiver to the open-drain bus and then connects it to other RX and TX pins of other transceivers. My understanding is that this should work with CAN bus, keeping in mind dominant bits have priority.

The only question remains: Is it OK to connect RX via open-drain circuit to TX of the same bus? I would say it is, but this is the part I am asking actually.

My circuit (drawn on tablet)

Image shows 3 different CAN transceivers connected in parallel. No matter on which bus signal is received, other 2 should see the same on their output.

This is schematics that works (verified), which I try to optimize. You can connect as many blocks as you want.

Answer 1

The TJA1050 CAN PHY can't be used to make a passive CAN hub/repeater.

If any device starts to pull the TXD is low to transmit dominant state on the CAN bus, the receiver is still active as it can monitor for collisions so it will soon after pull RXD low, which in turn will keep your TXD low and so the state latches low. At some point the PHY transmit timeout will activate and maybe release the RXD high. But you have three chips with all RXDs being able to drive the TXDs.

Most likely need an MCU with three CAN controllers to handle three CAN bus segments, and a microcontroller to forward messages between them.

Answer 2

There is/was a chip available that did the job of dealing with 1+2 CAN channels very well. It is the AMIS42700, which was discontinued. I have seen the above gate version with no need of an CPU. Looks great. There is a very similar design on the web from Otmar Schmid at oschmid.ch.