0.1 uF in parallel with larger >1 uF to reduce noise from IC

Question

Back in the day when we would use an electrolytic capacitor across the supply of a IC we would always put a 100nf Ceramic in parallel because (if I remember correctly) electrolytics had inherent inductive properties that would not suppress the HF noise on the power rails.

However, these days, high value ceramics exist (I regularly use 47 uF SMD in an 0805 package).

So does this mean, that I can get rid of the 100 nF (Ceramic) in parallel with the 47 uF (ceramic) caps because the 47 uF is ceramic and hence does not have the inductive properties of the electrolytics?

thanks

Answer 1

It is recommended to decouple with multiple caps but it depends on the circuit, chips overall design.

Higher caps, even MLC have higher SR, thus their filtering ability at higher frequencies drops significantly.

from here.

As an example, typically ADC for instance, which has a high-speed logic side and a low noise analog side often requires 0.1uF and 10uF decoupling on both their analog and logic supply. Same goes for some opamp, clock sources, etc..

Back in the day when we would use an electrolytic capacitor across the supply of a IC we would always put a 100nf Ceramic in parallel because (if I remember correctly) electrolytics had inherent inductive properties that would not suppress the HF noise on the power rails. However, these days, high value ceramics exist (I regularly use 47 uF SMD in an 0805 package).

It is true, caps got better and today's Ceramic has much lower SR than old electrolytic. But, as electronics has evolved, we now deal with much higher frequencies than in the old days, with microcontrollers often running in the 100Mhz range, clocks in the Mhz, and other buses in the Mhz range as well, without talking about CPU, RAM, etc.. Only using large ceramic caps will probably give you some issues and EMC problems.

If you look at reference schematics, IC will almost always have a 0.1uF decoupling cap, sometimes a 1uF or 10uF caps on some chips, and a few bulk caps.

Example from an opamp datasheet:

The EEVBlog has a very nice video about decoupling caps.

Answer 2

Multiple caps is actually frowned upon now because the caps can become resonant with each other. Use one cap only, at a decent small value to filter high frequencies.

Antiresonance of multiple parallel decoupling capacitors: use same value or multiple values?

Answer 3

The parasitic inductance in ceramic capacitors is largely dependent on the size of the package.

A 47uF ceramic cap is probably going to come in a much larger package than a 100nF ceramic capacitor cap and therefore have more parasitic inductance. But, if you can find 47uF cap in the same package as a 100nF ceramic cap, then the inductances will largely be similar and that one cap can serve as both the bulk decoupling capacitance and high frequency decoupling capacitance.

If you can't do this, then you either need to:

• use many small capacitors, each with sufficiently low inductance to decoupling the high frequencies, and use enough of them such that their total capacitance adds up to the capacitance required to decouple low frequencies. This can be a huge pain in the ass though but for some high speed chips there is no alternative.
• Parallel large capacitors with small ones, but this is not optimal because you are placing different series LC circuits in parallel which forms a tank circuit and causes resonant peaking. Not nearly as much of a pain in the ass as the first option and you can get away with it in lower performing circuits.

For decoupling high frequencies, the actual capacitance isn't as important as the lack of inductance, but for decoupling low frequencies the amount of capacitance is important.

Answer 4

It depends on your current spectrum noise and rejection specs. You cannot generalize anymore, unless spectrum limited <20MHz with low dI/dt. Low ESR e- caps are possible or multiple ceramics. Yet SMPS have special demands for low ESR spanning many f decades demanding multiple caps of different sizes.