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Why arent BJTs used with RISC architectures to produce very high speed relatively sparse CPUs? My understanding is that BJTs don't have the forward bias gate capacitance requirements of FETs which is a key consideration in clock and voltage settings on modern CPUs.

Power consumption and thermals aside is this possible? Please let me know if I am mistaken in any of my premise.

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  • \$\begingroup\$ Aside from ECL (worth study) have a look at bus drivers made from GTL (JEDEC) and GTLP (Fairchild derivative) based on BiCMOS from a decade ago or so. This isn't an answer. But GTL was used by Intel on the P II family backside bus, I believe. Worth reading about. \$\endgroup\$
    – jonk
    Commented Nov 5, 2020 at 9:34
  • \$\begingroup\$ thanks for your reply. \$\endgroup\$
    – Bots Fab
    Commented Nov 5, 2020 at 11:16

1 Answer 1

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Bipolar transistors:

  • on a chip, BJTs can't be made as small as MOSFETs, so any CPU made with BJTs would require an extremely large chip (making it expensive) or on a small chip you would be extremely limited in how many transistors you could use.

  • cannot be used to make power efficient logic circuits. We used to use TTL logic (based on BJTs) which uses a lot of power compared to CMOS (based on MOSFETs). If the circuitry on your smartphone was made using BJTs only, the phone would be the size of a truck and you would need another truck with a generator to power everything including the cooling system.

The fact that BJTs may have one or a few advantages over MOSFETs doesn't mean that the other huge disadvantages of BJTs for logic circuits suddenly disappear.

You cannot dismiss power and thermals (ad cost!) in this, because those are the reasons that CMOS is used for making processors and not Bipolar technology.

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  • \$\begingroup\$ Thanks for the information! I am pondering a pipeline that's all BJTs with registers etc. using traditional finfet design and wondering if performance could be realized in the higher end of the memory heirarchy/ALU. It's mainly theoretic but the thought of extremely fast pipeline is interesting. The speed differential to memory may be such that SIMD can be realized sequentially in a RISC pipeline hmmm. Thanks again. \$\endgroup\$
    – Bots Fab
    Commented Nov 5, 2020 at 9:34
  • \$\begingroup\$ It could be a SIGINT cluster in one of those hyperbolic cooling towers from the nuclear power plants they shut down \$\endgroup\$
    – Bots Fab
    Commented Nov 7, 2020 at 22:36

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