Why there is no shoot-through in CMOS logic gate?

Question

This picture is shown on Wikipedia.

From my understanding of shoot-through, I think this circuit will shoot-through every cycle of pulse and destroy itself.

1. Will it shoot through or are there any hidden elements to prevent it?
2. Can I make discrete CMOS logic based on this circuit? Or which circuit will work?

Answer 1

Yes, there is (some) shoot through, but it is not particularly significant.

1. In normal CMOS circuitry, the input signal transition is quite fast. Therefore the time during which both devices are (partially) on is quite small.
2. When there is shoot through, the total shoot through current is still less than the peak current the devices handle (because VDD is partitioned between both devices).
3. In CMOS circuits the current wasted by shoot through is usually smaller than that wasted by charging (or discharging) the load capacitances.

Answer 2

I've guided design teams, to produce control logic with minimal upset to VDD caused by logic transitions. The key

• use long channel CMOS --- may be 5nanosecond Tpd instead of 50pS Tpd

• operate the CMOS gates/FFs at reduced VDD (not 5 volts)

• have an RC filter between global VDD and the LOGIC VDD: 100 pf and 100 ohms

• have controlled_slew output driver(s)

Result? passed FCC emissions on first_test.

Answer 3

Here is an image of fairly low shoot-through current in the datasheet of a CD4069: