I am working on a PCB design. 50k PCBs will be produced.
SMD components: 100
Through-hole components: 25
I need to minimize PCB size. There are no high-speed signals or sensitive signals in the design.
I have two options:
Components on single-side PCB with multilayer (4 or higher) layout
Components on both (double side) sides of PCB with 2 layer layout
I need to clarify which costs less in production.
PCB size is not the only cost consideration and you need to consider recurring costs vs. one time (non-recurring) costs (some of the non-recurring may actually occur more than once for a 50k run).
Note that using double sided techniques rarely (if ever) yield a PCB half the size of a single sided part - in my experience you may get one that is perhaps 40% smaller if it is given lots of attention.
The non-recurring costs associated with PCBs includes the cost of tooling and the cost of solder stencils (which really are not that expensive although with a run of 50k you may need to use new ones after a certain number of runs which is very specific to the actual PCB).
Also in this category is test tooling which does have a certain amount of volume costs (50k boards will require the test tooling to have a certain amount of maintenance).
Another non-recurring cost is the fabrication and assembly documentation; poor documentation will incur recurring costs as you will be constantly fielding calls from the assembler and the specifics of the PCB may not be as controlled as you need. I suggest using the guidelines from IPC-D-326 (which incorporates IPC-D-325).
Recurring costs are:
Fabrication
Number of layers
Size (panelizing can reduce this depending on the specifics of the PCB)
Number of drill holes (often forgotten but can be a major cost driver)
Size of drill holes (to minimise costs keep the aspect ratio - the thickness of the PCB to the diameter of the drill - no higher than 8:1 and no smaller than 0.3mm)
The quality of the material (in particular Tg) as identified from IPC-4101. If you have high via densities you will need a relatively high Tg or you risk breaking the via barrels; this is a very common 'gotcha' that can destroy yields at assembly (the bare PCB test will not pick this up as it will only show up post reflow - the time above Tg is critical).
The PCB class (as identified from IPC-A-600)
Assembly
The assembly class as identified from IPC-A-610.
The number of passes through reflow and perhaps in your case selective soldering; basically there is a recurring cost for each process step required. You should also keep in mind that if a cleaning process is applied, it will normally be done for each pass through soldering.
The number of boards in a single panel; the more the better, in general (so you get more PCBs through for each process step although pick and place will have a higher cost but that is usually small compared to the gains from fitting more PCBs per panel).
Component density has an impact here as well; there will inevitably be some waste of components (usually the smaller parts) and the higher the density the higher that waste is typically.
Testing.
An automated test will have a non-recurring cost for the implementation and the lowest possible recurring cost (apart from no test at all). In terms of cost, it increases as you go from automated -> unskilled test labour -> skilled test labour on a per unit time basis.
There are other issues but these are the main ones in my experience and there is no single (or simple) answer; it depends on the specifics of your PCB. In the past where I have had the space for a single sided unit I have had the design done for both single sided and double sided design (incurring another non-recurring cost at the design stage) for high volume applications and sent both for quotations and the result can often be quite surprising.
In one case (where the design was always going to be double sided due to space constraints), the overall cost of fabrication and assembly was lower (by about 20%) when I increased the layer count from 14 to 18.
This significantly reduced the via count and eliminated high aspect ratio drills (the lower layer count had aspect ratios of up to 12 - the higher layer count maxed out at 10) and had the serendipitous effect of enhanced signal integrity (as I was able to use single layer routing for the majority of high speed signals).
[The methods required to run high speed signals across multiple layers while minimising losses is beyond the scope of this answer - suffice to say they are quite involved and use up more space than would otherwise be necessary]
