Does this circuit have marginal voltage level problem?

Question

As a research for the problem I described here I found this circuit by Maxim:

This is clock doubler, and must be a really good fit in my case as input frequency is very well defined.

However looking through the datasheets I found that MAX9010 outputs TTL levels, while 74VHC86 accepts CMOS levels (0.7 * Vcc). In general I can not find high speed comparator with CMOS outputs operating @ 5V.

Should I pay special attention to this issue - what are the conditions when circuit may fail producing proper clock?

Can you give feedback on the circuit in general? My assessment that it should work properly doubling 21.47727 MHz to 42.95454 MHz with R1=1k and C1=15pF (however for sure will need prototyping and adjustment in real life).

P.S. Last days I reviewed a lot of designs for managing clocks, and my feeling is that they in high degree a kind of "marketing articles" and not appropriate for the direct application - articles talk a lot about circuits' pros, but almost none state the cons (arising from propagation delays, frequency ranges etc) thus it is really bad idea to implement what is said directly without modelling and proper simulation for target conditions.

Update: as I suspected this circuit is an ideal design designed to work in ideal conditions. When built in real life, it does not function properly without investment into the following areas:

1. power must be maximally clean. Due to noise in the power rails voltage divider will have level fluctuating, causing spikes at the output of the comparator and false positives;
2. comparator may (will) sink some current from the voltage divider (reference voltage) at its positive input at the time of switching. It may also change reference point slightly;
3. RC with such small capacitance is very subject to be influenced by other capacitances around and EMI, changing tuned duty cycle (at best) or making x2 multiplication stage malfunctioning.

In addition, I have built this circuit using MAX999, but its LTSpice model is faulty. It is confirmed by the Maxim support, hopefully they will fix it.

I am going to drop this design, considering ICS501 instead.

Answer 1

However looking through the datasheets I found that MAX9010 outputs TTL levels, while 74VHC86 accepts CMOS levels (0.7 * Vcc).

That's a good spot and I agree with you - maybe you should inform Maxim on their dodgy circuit. Shame on them.

Should I pay special attention to this issue - what are the conditions when circuit may fail producing proper clock?

Yes, you can't use those two chips together without lowering the power rail on the 74 series. Maybe try a MAX999 - it's slightly faster on propagation time (4.5 ns) but, importantly, hits the rails on the output hence will drive the 74 chip.

Answer 2

The delay you require is only 25nS. I would consider simplifying your circuit to use two or all three of the other gates in the 74HC86 package to provide the delay, their nominal Tpd is 11nS at 5v into 15pF. Without extra capacitive loading, their delay might be a bit less. Their delay will be strongly affected by the rail voltage, so only use this method if the rail is well regulated.