added May 23rd
The concept is all parts have ESR so peak current and ripple current cause ohmic losses in regulation and ripple voltage. ![enter image description here](https://cdn.statically.io/img/i.sstatic.net/Vr1Rr.png)
Ripple cannot be eliminated, but it can be minimize by knowing the impedance of each part. Z(f) and look at transfer ratios. The biggest ripple reduction is to raise the switch frequency > 1MHz but this demands more expensive fast FETs and a good tight PCB EMI layout with care on stray ESL, C and orientation of loop currents. This reduces Δt a lot and reduces size of C since Zc=1/ωC This not something you can put on a breadboard. You just etch a small PCB or design it and buy 1 for $50.
Two estimates for Inductor ripple current depend on choice of L:
- \$\Delta I_L= (0.2 ~to~ 0.4) \cdot I_{OUT(max)} \cdot \dfrac{V_{OUT}}{V_{IN}}~~~~~ \$, if L is unknown
- \$\Delta I_L=\dfrac{ V_{IN(min)}\cdot D} {f_S} \cdot L\$
- for \$D=1-\dfrac{V_{IN(min}) \cdot η}{V_{OUT}}\$, for duty cycle,D and efficiency, η
Next, output voltage ripple generated by boost converter
\$\Delta V_{OUT}=ESR_{_{OUT} }\cdot \left \{ \dfrac{ I_{OUT(max)} } {1-D} + \dfrac{\Delta I_L}{{2}}) \right \} + \dfrac{I_{L(max)}\Delta t_{(max)}}{C_{out}}\$
\$C_{OUT}\$ RMS ripple current rating = 25% to 50% of \$I_{L(max)}\$
The biggest Cin load current is an abrupt startup with In=Vin/ESRin which for 10V/10 mohms from an ideal voltage source= 1kA surge current !!, so soft-start conditions need to be considered.
The biggest surge voltage on the output is a drop in load current.
Of course, wide load variations can be mitigated by various alternate design techniques such as ZVS and buck-boost switches.