Why would a buck converter IC fail and blow up?

Question

I have a deployed design in which we are experiencing a high (~4%) failure rate in the 12V to 5V step-down buck converter portion of the PCB. The buck converter's role in the circuit is to step down 12 V input (from a connected lead acid battery) to 5V, which is then fed to a USB-A receptacle for battery charging purposes.

All returned units have the same characteristic blown-up buck converter IC.

The IC is a TPS562200DDCT from Texas Instruments (reputable manufacturer, so I hear)

Here is the datasheet.

Here is a picture of a failed unit:

Here is the schematic:

Here is a look at the PCB design file for that section of the board:

In analyzing the failure of the buck converter IC, I think that you can ignore the low battery cutoff circuit. That portion of the circuit simply uses a reference voltage and low-side pass FET to cut off the battery's negative terminal from the rest of the circuitry when the battery's voltage drops below 11 V.

It seems to me that an external short circuit on a device connected to the USB receptacle would not be a culprit, since the TPS562200DDCT has overcurrent protection built into it:

7.3.4 Current Protection The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored during the OFF state by measuring the low-side FET drain to source voltage. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN, VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current IOUT. If the monitored current is above the OCL level, the converter maintains low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until the current level becomes OCL level or lower. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over current condition exists consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the switch current is not above the lower OCL threshold, the counter is reset and the OCL threshold is returned to the higher value. There are some important considerations for this type of over-current protection. The load current is higher than the over-current threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the VFB voltage falls below the UVP threshold voltage, the UVP comparator detects it. Then, the device shuts down after the UVP delay time (typically 14 μs) and re-start after the hiccup time (typically 12 ms).

So, does anyone have any idea how this could have happened?

EDIT

Here is a link to a reference design that I used to come up with component values and operating points for the buck converter using TI WEBENCH Designer:
https://webench.ti.com/appinfo/webench/scripts/SDP.cgi?ID=F18605EF5763ECE7

EDIT

I have done some destructive testing here in the lab and can confirm that I get a very similar-looking pile of melted plastic where the Buck converter used to be if I plug in the battery with reverse polarity. Since our choice of battery connector does provide a relatively high chance of accidental reverse polarity plug-ins (say, 4% chance --> wink wink), it would seem likely that this is responsible for the majority of the failures we observed.

Answer 1

I suspect overvoltage on the chip, with a second possibility inductor saturation as @oldfart suggested in a comment.

Your supply bypass is an electrolytic capacitor, a little far from the chip and is a small electrolytic so it has a relatively high ESR (and, unfortunately, an ESR that will increase as the capacitor ages).

The input ripple current, in combination with stray inductance from wiring can lead to overvoltage on the chip input. I suggest testing it with a supply with long wires and test at the limits of the supply range. Put an oscilloscope on the power rails and see how big the spikes are. A ceramic 22 µF capacitor with an electrolytic (e.g. 1000 µF/25 V 105 °C) in parallel, if you have room, would be much better. Check that the "22 µF" ceramic is over 10 µF at the maximum operating voltage. It should be as close as practical to the chip. And, of course, it's best to follow the suggested layout practices in the datasheet as closely as practical.

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Inductor saturation is a different issue- it would tend to occur at minimum supply voltage where the input current is maximum. You can test it by bypassing your undervoltage lockout and reducing the input well below the minimum normally expected. Symptoms would be excessive power dissipation in the chip.

Answer 2

Problem: cheap high ESR capacitor and ignoring design application notes.

Edit

Ignoring car applications if it does not apply, take note of requirement for low ESR capacitors.

For this design two TDK C3216X5R0J226M 22 μF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.

Note that 22 μF * 2 mΩ = τ = 0.044 μs is excellent ceramic performance, where low ESR electrolytic capacitors are < 1 μs and general purpose electrolytic capacitors >> 100 μs. Since f >> 50 kHz this is critical for regulation and improved with three of the suggested parts in parallel.

It is impossible to achieve this low ESR*C = τ in an aluminum electrolytic capacitor, even with ultra-low ESR types. This is why ceramic is used in this design.

If the ESR is too high and reactive step loads are applied then there is more chance for instability, higher ripple voltage, and overshoot.

If you do not have automotive design or test specifications or a DVT test plan with stress testing, this design had not been completed properly.

Answer 3

The datasheet recommends C4 to be a low ESR ceramic capacitor (20 µF to 68 µF). You seem to have a 22 µF electrolytic. All datasheet examples show two 10 µF in parallel. The actual value probably depends on the frequency. I have no idea if this may or may not be a problem. But...

I've had MC34063 fail, because the input capacitor was inappropriately low or had high ESR. Failure usually occurred at power off, but that may not be relevant here.

Answer 4

Through destructive testing here in the lab, it would appear that the most likely cause of this melted pile of buck converter innards was application of reverse polarity to the buck converter.

Thanks to all for your insights, I will definitely be using them to improve the next iteration of this design.

Answer 5

I would suggest that the very small part is getting way to hot when a load is placed on it and just burns up. The board layout also does not show much in the way of using copper as a board level heatsink for the part.

You may need to either come up with a heat spreader, use a package that has an integrated thermal pad and/or find another part in a lot beefier package.

Answer 6

If you intend to re-visit the design, choosing a part with a more tightly controlled Enable threshold would allow the whole low voltage cut-off circuit to be replaced by a simple potential divider on the EN pin. This cost saving would pay for the new device and might give some budget for some protection components. The TPS562200 could current limit at up to 5.3A. The inductor is probably highly saturated by then.