Cycle-Time/Latency optimization in synthesis of digital circuit question

Question

I've been trying to build a solid understanding of digital synthesis. And I've found a useful book (this one) for it, specifically I'm into "Architectural optimization" now (section 4.5). In such section it is explained the trade-off among Area/Latency/Cycle time, the explanation is then divided in three subsections: Area/Latency; Cycle-time/Latency; Cycle-Time/Area. Basically it is consider the relationship between the two variable assuming the third is fixed.

I have trouble understanding a the Cycle-time/latency tradeoff here it is what the book reports:

We consider bound sequencing graphs that are either representative of initial circuit specifications or derived by binding. Let us consider resource-dominated circuits first. For each value of the cycle-time of interest, the corresponding execution delays of the operations can be derived and a minimum-latency schedule computed. Alternatively, scheduling with chaining can be performed by considering the propagation delays of the resources. Let us consider now the case in which we are interested in the minimum cycletime compatible with a given latency. When the resources are combinational in nature, the problem reduces to determining the register boundaries that optimize the cycletime. This problem has been referred to as retiming, and it is dealt with in Section 9.3.1. The formulation and its solution can be extended to cope with sequential resources by modeling them as interconnections of a combinational component and register. These considerations can be applied to general circuits when the binding of the multiplexers and registers is specified and fixed and when the wiring and control-unit area and delay can be approximated as constant or neglected. Under these assumptions the overall area is constant. Then, the multiplexers can be considered as additional combinational resources with their appropriate delays. The cycle-timet/latency trade-off points can he determined again by scheduling with chaining or retiming.

I don't really understand why there's the need for to study the tradeoff cycle time/latency, I'll try to highlight what I don't understand:

For each value of the cycle-time of interest, the corresponding execution delays of the operations can be derived and a minimum-latency schedule computed.

It sounds like in this sentence that the cycle time can some how affect the resource scheduling and I don't understand why... If define time labels, these are independent from the cycle time and then I can perform resource scheduling anyway, since it is cycle-time independent I assume a minimum latency schedule is the same whatever the cycle-time actually is.

Let us consider now the case in which we are interested in the minimum cycletime compatible with a given latency

Again here, I don't get the relations that there's between cycle-time and latency, especially I don't get the "compatible". The cycle time cannot be longer than the latency, but for a given schedule the cycle-time should be easy to derive.

I believe if I understand what the actual point is in the sentences I pointed out the rest should be easy to understand.

Answer 1

Consider you have an application where to get the answer, you need to pass through 10 gates in series, and each gate has a delay of 10nS.

If you ask for a 150nS cycle time, then you can string all the gates together sequentially in one clock cycle, and your latency will be one cycle.

If you ask for a 80nS cycle time, you must break the sequence of operations into two, and register the intermediate results. Now your latency is two clock cycles.

If there is some other way to arrange the resources, perhaps into two parallel chains of 5 gates, with further logic to split and combine the answers (so more area) or higher power components that have smaller delays (so more power), we may be again able to fit all the processing into one cycle.