I am trying to implement a small RISC CPU (without branch prediction and register renaming.) I want to give it a fully associative cache (I and D caches.)
Everything is going well, but now I must understand how to decide which entry to discard. I use a CAM to store tags (page number) and find cache entries. Upon miss I can handle the miss via a MMU unit etc.
I already know how to do direct mapped cache.
How can I implement an LRU policy on the cache?
The best solution I found would need N (=number of cache lines) clock cycles to compare each line and find the least recently used entry to be evicted. That’s very slow.
Time to evict the page to external RAM + time to choose the page = too many clock cycles.
Is there any way to decide which page is the least recently used one in one clock cycle?