Is it possible to use a 2 flip-flop synchronizer for reset?

Question

I have seen designs for asynchronous resets synchronization like in this picture:

I think I understand the asynchronous assertion and synchronous deassertion that this design delivers.

I am not certain that I understand why this circuit is used and not a 2 flip-flop synchronizer.

My current hypothesis is that if a designer uses a 2 flip-flop synchronizer the assertion of the synchronized reset at the output will be delayed for 2 clock cycles in case of no timing violations. Or 1 Clock cycle in case the first flip-flop enters metastability due to timing violation and it resolves to the level of an asserted reset in the next clock cycle.

This delay would obviously break a requirement for the synchronizer output to reset the design immediately on assertion of the reset at the synchronizer input.

My question is for the scenario where the requirements allow a delay of several clock cycles.

1. Is it still necessary to use a reset synchronizer instead of a 2 FF synchronizer?
2. If the answer to 1 is yes, why?

Answer 1

The purpose of this structure unlike a simple 2FF synchroniser is that you get true asynchronous assert whilst maintaining the metastability protection on deassert. There will be a non-deterministic latency between input and output reset deassertion is either case as is intrinsic to clock sychronisers of any kind (it could be one cycle, it could be two).

Unlike the 2FF case, in this circuit when the input reset goes high, the downstream reset immediately follows (give or take some intrinsic RST->Q delay in the flop). This will happen regardless of the state of any other input signal. Critically (and helpfully) this also means regardless of the clock.

Consider a system where your clock comes from a PLL output. That clock output may or may not be present or stable depending on whether the PLL is actually locked (the same goes for any clock signal to be honest).

With a 2FF synchroniser only, if you failed to assert the reset signal before the clock disappeared (or if it hasn't yet appeared), there is no way to reset the downstream system - because the 2FF synchroniser has synchronous assert and therefore cannot forward the signal. With this structure that problem is avoided because even if the clock is not present, the output reset will assert.

Answer 2

It will be delayed for at least one clock cycle, because you don't know the relationship between the rising (deactivating) edge of the reset and the rising edge of the clock -- worst case the reset is deasserted immediately before the clock edge.

The one cycle delay means that any combinatorics behind FFs that are reset from R have one full cycle to settle, so the FFs they feed will not pick up a metastable state.