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Background

The TI TLC6983 LED driver datasheet provides decoupling capacitor recommendations for the IC and LED supply pins, in 10 : Power Supply Recommendations:

Decouple the VCC power supply voltage by placing a 0.1-μF ceramic capacitor close to VCC pin and GND plane.

Depending on panel size, several electrolytic capacitors must be placed on the board equally distributed to get well regulated LED supply voltage VR/VG/VB. The ripple of the LED supply voltage must be less than 5% of their nominal value.

Issue

If the same voltage bus is used for V.cc and V.led.R (which is recommended by the datasheet), there is a recommendation for:

C_V.cc    = 00.1 [µF] (per datasheet)
C_V.led.R = 60.0 [µF] (per datasheet ripple requirements for my specific case)

It is generally recommended to not mix capacitors due to antiresonance.

Question

Should the V.cc pin:

  • Use the V.R bus track/zone including its 60.0 [µF] capacitor?
  • Use the recommended 0.1 [µF] capacitor, but keep its track separate from the adjacent V.R bus track/zone, (as depicted below).

enter image description here

Capacitor information (Requested by respondents)

C.V.cc = 1x 00.1 [µF] (KEMET C0402C104K8RAC- 10% X7R 10V 0402)
C.V.led.R = 4x 22.0 [µF] (KEMET C1210C226K4PAC- 10% X5R 16V 1210)

Here is the chosen cap and relatively similar, cost-practical alternatives.

All have roughly similar ESR at f.refresh.min = 3.8k [Hz]. Ceramic: Lower height (desirable for tight board-to-board connection). Better high frequency performance. Radial Can: Far cheaper. No |Z| data provided.

A: 4x KEMET C1210C226K4PAC :

Type     : Ceramic
C.actual : 4x 20.6 @ 4.0 [V] = 82.4 [µF]
C.tol    : ±10% ±X5R
V.dc.max : 16 [V]
Size.net : 6.36 x 4.65 x 2.8 [mm] (duplicated on pcb bottom)
$        : 4x 0.119 @ (qty. 2000 • (4+4+2) • 4 ) = 0.476

B: 1x KEMET A700V686M006ATE028:

Type     : Aluminum Polymer
Life     : 2000 Hrs @ 105°C
Package  : IC
C.actual : 1x 68 [µF]
C.tol    : ±20%
V.dc.max : 6.3 [V]
Size.net : 7.3 x 4.6 x 6.0 [mm]
$        : 0.477 @ (qty. 2000 • (1+1+1) • 4 )

C: 1x KEMET A766EB127M0JLAE022:

Type     : Aluminum Polymer
Life     : 5000 Hrs @ 105°C
Type     : Radial can
C.actual : 1x 120 [µF]
C.tol    : ±20%
V.dc.max : 6.3 [V]
Size.net : 6.6 x 6.6 x 6.0 [mm]
$        : 0.102 @ (qty. 2000 • (1+1+1) • 4 )

A & B:

enter image description here

enter image description here

C:

|Z| vs Frequency data not provided, only ESR. enter image description here

Metainformation

Continued from this question.

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  • \$\begingroup\$ I'd like to know more about the caps: type and size (if not MLCC, a datasheet would be nice to get the ESR). Why are all the vias unconnected? If the brown layer is a ground plane, they should be connected... I mean, I assume "RTN" is "GND", right? \$\endgroup\$
    – bobflux
    Commented Apr 18 at 15:18
  • \$\begingroup\$ @bobflux : I showed a separate layer (scanline3, net seen to the bottom-right) to fully depict the via perforations. I tried to minimize slotting by keeping perforations sufficiently distant. Capacitor info inbound. \$\endgroup\$
    – kando
    Commented Apr 18 at 15:25
  • \$\begingroup\$ @bobflux : Capacitor info posted, along with comparable electrolytic alternatives, in good faith of your original suggestion. \$\endgroup\$
    – kando
    Commented Apr 18 at 16:39

1 Answer 1

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For decoupling, high frequency impedance of a MLCC is determined by inductance, which is determined by physical size and mounting inductance (vias). Therefore, all caps of the same footprint will all behave pretty much the same at high frequency no matter what the value is. 100nF isn't a magic value, it's just the standard issue datasheet "rubber stamp" value but nothing stops you from taking it as a minimum.

If you have just one chip and put 10µF//100nF with both having the same size and located at the same spot, the 100nF will not be very useful. The point of low value caps is they're cheap and small so if you have lots of power pins on your chip you can put lots of caps.

When two caps are wired in parallel they form a series RLC circuit:

enter image description here

The two caps are actually in series in this circuit, so it is equivalent to a series RLC circuit with one capacitor equivalent to the two caps in series. Thus you can use the usual formulas:

  • \$ C = \frac{1}{1/C_1 + 1/C_2} \$

  • \$ R = ESR_1 + ESR_2 \$

  • \$ L = ESL_1 + ESL_2 + layout \$

Then to avoid ringing you need the damping factor to be >1 or at least not too low:

\$ \zeta = \frac{R}{2} \sqrt{\frac{C}{L}} \$

Inductance depends mostly on mounting, in your case you have good via placement on the big caps, and presumably they are connected with planes or at least wide copper pours, so you can use about L=2-3nH. ESR comes from the datasheet or manufacturer curves. ESR of the big caps is in the milliohm range, so it is usually negligible compared to the smaller one.

Or you can just spice it, here I used 100nF and 1µF with generic ESR. Higher value has lower ESR. Current source with AC 1 means plotting V is the same as plotting impedance in ohms.

enter image description here

Or you can use Kemet's tool:

enter image description here

When inductance is low thanks to planes, as you see on the impedance plot, it's fine. If you feel extra paranoid, you can use the highest capacitance that will fit in 0402 to lower the peak, but it'll probably work absolutely fine with 100nF.

I guess you can connect the two caps together on top layer, along with all the pins on VR, it probably won't change anything.

You could also rotate the 2 large caps 90° to route the VR copper pour on top layer.

Like this you have a lot of copper for V.R/VCC:

enter image description here

Or like this, but the vias will have to be moved around to leave space for vertical traces:

enter image description here

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  • \$\begingroup\$ I have a clarification : I wasn't suggesting connecting all of the caps together on the top layer; I was asking whether I should use a 0402 separate on the top layer from the 4x 1210s (as shown) or if I should ditch the 0402 entirely and increase the 4x 1210s zone to include the V.cc pin that the 0402 is shown to connect to. \$\endgroup\$
    – kando
    Commented Apr 21 at 15:44
  • \$\begingroup\$ Rephrased: Would using a separate track with a tiny package cap potentially insulate V.cc from any noise created by all of the transient activity of V.R's consistently dynamic load, creating a much steadier voltage on V.cc? \$\endgroup\$
    – kando
    Commented Apr 21 at 15:44
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    \$\begingroup\$ It's all on the same plane, so the only difference would be a tiny bit of inductance, and it's not a GHz CPU... 0402 probably won't be necessary... in fact you could put the 4x 1210 caps on toplayer, with the 2 that were on the bottom moved in place of the 0402 cap, and use plenty of copper for V.R \$\endgroup\$
    – bobflux
    Commented Apr 21 at 17:39
  • \$\begingroup\$ The other side of the chip will require top and bottom for V.blue and V.green in all cases. Further additional recommendation has been made to duplicate ceramic caps on the bottom-side to cancel out audible noise made by the ceramic cap (relevant to me for a handheld consumer device) \$\endgroup\$
    – kando
    Commented Apr 21 at 17:44
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    \$\begingroup\$ OK then if they don't get in the way of your layout on the bottom then no problem. Good point about noise. \$\endgroup\$
    – bobflux
    Commented Apr 21 at 17:45

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