Output stage filter of a buck regulator and ESR

Question

I am trying to design a two LC stage output filter on a buck converter. And as the needed peak to peak ripple has to be pretty low ~ 1 mV, the overshoot and undershoot need also to be pretty low, I have to be fairly precise on the design of this output filter

At the beginning, I was thinking that I could have a pretty good estimation of the capacitors by looking at the datasheet of the "real" capacitances due to bias voltage and temperature dependency. But actually this is not so easy! The data are not so easy to find and apparently each ceramic X7R capacitor has its own curves in function of bias voltage and temperature. It makes the estimation of the peak to peak ripple not so easy.

Also and this is the subject of the question, there is a certain ESR for every capacitors. I was thinking that the ESR was a constant value, but it appears to not be the case as the below graph is showing:

It makes me confused about what is really ESR. Whatever is ESR, it seems that it is varying according to the frequencies. So suppose I have a step load on my output filter, how can I know what would be the undershoot as the ESR is not constant over the all frequencies spectrum of the step load.

Also, sometimes it is not possible to have the graph above provided by KEMET website, and so it is more difficult to estimate what would be the ESR of a ceramic capacitor. It is important to know what is the ESR of my output stage filter as it will have an impact on the undershoot/overshoot of the voltage after a step load. It will also have an impact on stability. I was thinking that It would be possible to estimate the ESR with dissipation Factor (DF) but it is not really simple as it is as the dissipation factor is given for a certain frequency, generally @ 120 Hz. In my case, the step load has an infinite content of frequencies and so my ESR is not equal to the ESR that I would have @ 120 Hz and in any case for an SMPS working at more than 100 kHz as a switching frequencies it has no sense to have the DF @ 120 Hz for a ceramic capacitor...

So the question is how to estimate ESR of capacitors for an output stage filter? What hypothesis I have to take?

Thank you very much,

Answer 1

It makes me confused about what is really ESR. Whatever is ESR, it seems that It is varying according to the frequencies.

KEMET uses SPICE models to plot ESR and Impedance (Z) graphs. Following is the SPICE model for a 10u/50V 1206 X7R capacitor:

.SUBCKT C1206X106K3RAC 1 6
*Temp = 25°C, Bias = 0VDC, Center Frequency = 10000 Hz
*KEMET Model RLC Cerm
R1 3 4 0.0437875837087631
R2 2 5 0.810000002384186
R3 1 6 100000000
L1 1 2 3.70000002858362E-11
L2 2 3 7.03000005430887E-10
C1 4 6 9.63658385444433E-06
C2 5 6 6.00000023841858E-13
*ENDS

^{simulate this circuit – Schematic created using CircuitLab}

L1 is ESL, R3 represents self-discharge, C1 is the actual capacitance, etc.

So, apparently, KEMET's ESR plots are actually the equivalent of ESL, ESR, and other parasitic components e.g. \$R_e=\sqrt{L^2+R^2}\$. This makes the ESR plot frequency-dependent.

As for your main question, normally, overshoot/undershoot (OS/US) amounts depend on the output capacitance, crossover frequency, and the amount of step change i.e. \$\Delta I_O\$. If you want to get a very low OS/US as well as 1mV of ripple then

• Crossover frequency should be very high: This will cause noise issues. Practically, 1/5 to 1/10 of the switching frequency is a good starting point. This brings a limit to the OS/US amount.
• Output capacitance should be very high: This will make the ripple very low but will cause startup/shutdown issues.
• Total ESR should be very low: This could be possible with MLCCs but you may end up with a ridiculous number of MLCCs connected in parallel.

So the question is how to estimate ESR of capacitors for an output stage filter? What hypothesis I have to take?

That's a difficult question for me to answer because such low ripple anf OS/US have never been a requirement for my designs or the designs I was involved/took part in. I usually neglect ESR's effect on OS/US. Instead, I approach ESR more seriously for ripple.

A general formula for OS/US amount:

$$ \Delta V = \frac{\Delta I_O}{2\pi \ f_C \ C_{OUT}} $$

This explains the relation between the OS/US amount and the crossover frequency, and the output capacitance.

For very low ripple, maybe you should consider multi-phase converters or linear regulators instead.

Answer 2

ESR is the effective series resistance. Note the word effective because, it isn't the actual internal series resistance (as seen at resonance) but, an equivalent series resistance representing all the losses of the capacitor at a particular frequency. See this quote from Wiki - ESR: -

In a non-electrolytic capacitor and electrolytic capacitors with solid electrolyte, the metallic resistance of the leads and electrodes and losses in the dielectric cause the ESR.

Note the highlighted text: losses in the dielectric. So ESR is not just the internal series resistance but, a combination of both losses.

So the question is how to estimate ESR of capacitors for an output stage filter? What hypothesis I have to take?

If you can live with the parallel resistive dielectric losses (of which the equivalent resistance should be massively greater and less significant than your actual load) and, are only interested in knowing the true series resistance of the capacitor, then use the figure at self-resonance.

As a side note, what Kemet plot at lower frequencies (below resonance) is based on the typical dissipation factor (about 1.3%) thus, at 1 kHz, you see this: -

The ratio of their ESR figure to the capacitive reactance is 0.204/16.01 = 1.27%. That particular capacitor has a maximum DF of 3% hence ~1.27% is what they have decided is a typical value. And, remember, DF also tells you what the equivalent dielectric losses are at non-self-resonant frequencies: -

$$DF = \dfrac{ESR}{X_C}$$

Answer 3

If you know either the self resonant frequency or ESR@120 Hz and ESL, I would model it as an ideal capacitor with series L and C. If the impedance plot is a nice V from the manufacturer or your own measurement, that model should be very close to reality.

If not, perhaps pick out the fundamental frequency and model it around that.

Not what you asked, but at 1 mV ripple requirement, I would look at and LDO to follow your buck.