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In CMOS-based analog computing, there always are mixture of analog and digital parts. For example, the computation is performed in analog domain and the storage of on-chip data in performed in digital domain using on-chip SRAM.

However, as the technology for analog computing is lag behind the digital computing, the analog chip always uses a out-of-date technology (e.g. 28 nm), I wonder can we use 14 nm technologies to design the chip, but the analog parts are just designed using 28 nm (this is because the 14 nm technologies can use 28 nm transistors)?

Is there a CMOS-based analog compute chip that uses hybrid technology nodes? (e.g. 14 nm for digital part such as SRAM and 28 nm for analog part)

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    \$\begingroup\$ Combining different technology nodes is the job of packaging. \$\endgroup\$ Commented Aug 16, 2023 at 14:32
  • \$\begingroup\$ Is it possible to combine two different technology nodes in a finer-granularity such as in the same chiplet? (For example, use 14nm 6T SRAM cell and use 28nm analog in-memory-multiplier) \$\endgroup\$
    – Yu Qian
    Commented Aug 17, 2023 at 2:55
  • \$\begingroup\$ That is not possible. \$\endgroup\$ Commented Aug 17, 2023 at 14:29
  • \$\begingroup\$ Sorry to hear that, but thanks for your replying! \$\endgroup\$
    – Yu Qian
    Commented Aug 23, 2023 at 3:02

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This is problem that has been plaguing analog circuits in deep submicron technologies. Getting worse with each node reduction.

AFAIK, the so-called "chiplets" have been invented in order to accommodate many dies within one package, thus optimizing the usage of different technologies for different purposes (analog, digital, etc.).

Some months ago I attended a seminar were they said they're trying to standardize the technology, as the interfacing between dies is not standard.

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  • \$\begingroup\$ Thanks for your replying ! I am conducting a survey about analog computing for NN acceleration, and I find a way to design analog computing cell is to stack multiple SRAM bits (e.g. 32 bits) with the same analog multiplier (such as the paper titled "A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips "). I am wondering can we shrink the process of the 32-bit without shrink the process of the analog multiplier ? (as shrinking analog circuit will affect the accuracy) \$\endgroup\$
    – Yu Qian
    Commented Aug 17, 2023 at 2:50
  • \$\begingroup\$ @YuQian as far as I know, only the chiplet technology can give you a way out by combining different dies in one single package and interconnecting them. Combining 2 different processes in one single substrate is very difficult, or probably practically impossible due to each process having different manufacturing steps/parameters/etc. \$\endgroup\$
    – Designalog
    Commented Aug 17, 2023 at 6:21
  • \$\begingroup\$ Also, 3D integration, like through-silicon vias, etc. \$\endgroup\$
    – stevesliva
    Commented Aug 31, 2023 at 21:23

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