I searched and read many similar questions, but did not find a specific answer for how to calculate the correct value for a pulldown resistor for a MOSFET's floating gate. It seems like everyone dodges the question with a 1K, 10K, or 100K "ought to work".
If I had an N-Channel IRF510 and I was going to run the gate from 9V to switch a \$V_{DS}\$ of 24V at 500mA, what value should I use for the gate's pulldown resistor and how did you calculate that value?
Here is a quantitative way to determine the boundaries of acceptable gate termination resistance \$R_g\$ for power MOSFETs .
This will be a lazy lazy lazy (\$L^3\$) approach. So:
The intent of a (\$L^3\$) approach is get maximum insight/usefulness with minimum effort, by using a model that is simple as possible but still meaningful.
Model is a simple capacitive divider with resistive pull down. \$V_{\text{gs}}\$ was solved for in the frequency domain, and then inverse Laplace transformed for time domain.
Three operating conditions are analyzed using this model:
After setting \$R_g\$ = \$\infty\$:
\$V_{\text{gs}}\$ = \$\frac{C_{\text{gd}} V_{\text{ds}}}{C_{\text{gd}}+C_{\text{gs}}}\$
So, in this case, \$V_{\text{gs}}\$ is just a scaled version of \$V_{\text{ds}}\$, and the scale factor is the capacitive divider of \$C_{\text{gd}}\$ and \$C_{\text{gs}}\$. For the IRF510:
\$V_{\text{ds-max}}\$ = 100V
\$C_{\text{gd}}\$ = \$C_{\text{rss}}\$ = 20pF
\$C_{\text{gs}}\$ = \$C_{\text{ciss}}\$ - \$C_{\text{gd}}\$ = 135pF - 20pF = 115pF
\$V_{\text{gth-min}}\$ = 2V
For a drain to source voltage greater than 14V, \$V_{\text{gs}}\$ will be greater than the 2V threshold and the part will start to conduct. It doesn't matter how the voltage appears on the drain, just that it is there. Pretty obvious why nobody ever leaves a FET gate unterminated.
Allowing \$R_g\$ to be a variable finite value:
\$V_{\text{gs}}\$ = \$C_{\text{gd}} V_{\text{dsSlp}} R_g \left(1-e^{-\frac{t}{R_g \left(C_{\text{gd}}+C_{\text{gs}}\right)}}\right)\$
\$V_{\text{dsSlp}}\$ is the slope or linear ramp forcing voltage (in volts/second) across the drain to source. If \$V_{\text{ds}}\$ rises from 0 to 25V in 2 milli-seconds, \$R_g\$ will need to be less than 11 MOhms for \$V_{\text{gs}}\$ to remain below the 2V threshold and remain off.
Such slow rates of change (in the 1 to 10 milli-second range) for \$V_{\text{ds}}\$ are why Olin Lathrop can correctly say \$R_g\$ values of 1kOhm, 10kOhm, or 100kOhm ought to work. So, yes for a passive pull down to keep a FET off during system startup or other seldom switched low dV/dt application, almost any kilo-Ohm resistor will do.
Why even waste time looking at this? If that's all there is we can all just roll over, go back to sleep, and be happy. But, there's a lot more to it, so let's look at a little of that next.
Nearly all FETs end up being frequently switched, between 10KHz and 500KHz, with short rise and fall time \$V_{\text{ds}}\$ transitions. Most FETs will be turned off in 20 to 100 nano-seconds, and this is where gate termination becomes important. Let's look at the IRF510 with \$V_{\text{ds}}\$ rising linearly from 0 to 25V in 50 nano-seconds. Using the equation in conditon 2 above:
\$V_{\text{gs}}\$ = \$ \text{(20pF) }\text{(25V/50nsec) }\text{Rg} \left(1-e^{-\frac{\text{50 nsec}}{\text{(20pF + 115pF)} \text{ Rg}}}\right)\$
So, plugging in a value of 270 Ohms for \$R_g\$ gives \$V_{\text{gs}}\$ ~ 2V. That would be the highest value of \$R_g\$ that could be used without the FET possibly turning back on.
\$R_g\$ greater than this maximum value allows the FET to be turned on a little or a lot, depending on the energy forcing \$V_{\text{ds}}\$. FET could turn on just enough to leak current and dissipate power, but showing no real effect on \$V_{\text{ds}}\$, or could turn on enough to cause \$V_{\text{ds}}\$ to drop, which in the right conditions can cause oscillation.
Clearly, the higher the peak value or transition rate of \$V_{\text{ds}}\$ the lower the gate circuit resistance must be.
Why not just make \$R_g\$ zero, or as small as possible?
So far in this analysis, the gate circuit is dominated by resistance, but there is also inductance in the gate circuit. If gate resistance is minimized, gate inductance becomes dominant in circuit dynamics, and with \$C_{\text{gs}}\$ forms an LC resonant circuit. LCR circuits with Q > 1 become increasingly ringy, which is a problem for FET gate control if charge is injected through \$C_{\text{gd}}\$ from \$V_{\text{ds}}\$ or also from switching waveform from the gate drive . For example, an LCR circuit with a Q of 2 will ring to about 1.5 times its driving voltage. For a gate drive with a 14 V source, a Q of 2 would be enough to damage the gate of most FETs.
For a series LC resonant circuit :
Q = \$\frac {Z_o} {R}\$ and \$Z_o\$ = \$\sqrt {\frac {L} {C}}\$
Let's look a a specific case with the IRF510. Including routing and package inductance, the gate circuit could easily have 11 or 12 nH of inductance. Recall that the IRF510 has a \$C_{\text{gs}}\$ of 115pF, so \$Z_o\$ would be about 10 Ohms. Matching \$R_g\$ to \$Z_o\$ would give a Q of 1, which would be the maximum Q for non-overshoot of drive waveform. Minimum \$R_g\$ should be greater than \$Z_o\$.
Consider this to be the minimum knowledge needed about gate circuit resistance in MOSFETs.
1 kΩ, 10 kΩ, or 100 kΩ ought to work.
Think about what the purpose of a pulldown is and when it matters. During normal operation the gate is generally actively driven both ways. A pulldown resistor does nothing useful then, and a best doesn't get in the way.
Usually the purpose of a pulldown is to keep the FET off during startup while the active gate drive circuit is high impedance. This could happen, for example, if the gate is being directly driven from a microcontroller pin. It may be 10s of ms before the micro's clock starts running and it gets around to executing the instructions that put the pin in a known output state. That could be bad if the FET should only be on for a few µs at a time to prevent some inductor from saturating, for example. In cases like that, not only could the FET waking up on cause excessive current, but that excessive current could actually prevent the supply from coming up all the way, essentially latching the circuit in crowbar mode indefinitely.
So what are the criteria for deciding the value of the pulldown? On one end, the resistance needs to be low enough so that the gate is discharged in time, and can be held in the low state despite capcitive coupling from startup transients. The gate of a FET has very high resistance and mostly looks capacitive. Even a large resistor can eventually discharge the gate capacitance. The limiting factor there is how fast the device might be turned off and then back on again. Usually this isn't the issue though. Keeping the gate low despite startup transients is much harder to judge since it's almost impossible to know where these transients may be coming from and how strongly they will couple onto the gate node. This is why you see such a range. Nobody really knows what's needed, so they experiment and derate, or more likely, pick a nice number. Different people's idea of nice varies.
On the other end, you don't want the pulldown to draw significant current that would otherwise go to driving the gate high quickly or at all. If you're using a FET driver that can source 1 A during switching, the extra 10 mA from 1 kΩ pulldown is pretty much irrelevant. On the other hand, if the gate is being driven straight from a micro pin, then the extra 5 mA of a 1 kΩ pulldown could be a significant inconvenience. In that case, 10 kΩ would be better. It's rarely necessary to go higher than that, but in some low power circuits where the FET is on for long periods of time you might want 100 kΩ.
So like I said, 1 kΩ, 10 kΩ, or 100 kΩ ought to work.
