As mentioned in Andy's answer, zener leakage is low until it's near conduction. This is fine at nominal voltage.
There is still the marginal case where, if voltage rises slowly, a relatively long time will be spent on the knee of conduction, where, say 0.1mA flows into the gate, and say that causes an anode current of 10mA, insufficient to trigger the SCR, and it sits there simmering at 60V * 0.01A = 0.6W. Would that cook it off? Perhaps it doesn't trigger until Ia = 100mA. Would it fail then?
Note that, below threshold, an SCR acts just like a BJT. hFE varies wildly, being low at low currents (recombination dominant), and divergent at high currents (up until the point it latches on and hFE is undefined). So we can model the slow-rise case as if it were a BJT of hand-waved gain.
Unfortunately, datasheets do not provide sufficient information to determine whether an SCR will be safe in a slow-rise scenario such as this. The better design practice is to avoid such behavior instead.
The R+D gate network seems peculiar to me, allowing ~full leakage into the gate. More precisely, it acts as a crude current mirror, where a diode (ideally, a diode-strapped transistor) biases the base of a transistor. The rectifier and SCR will be very different from each other (meaning offset and gain, and tempco, won't be predictable), but the overall cancellation-of-logarithms function remains.
Better is to introduce external hysteresis, add a schmitt trigger or whatnot. Consider this for example:
From: https://www.seventransistorlabs.com/Images/Crowbar2.png (links to my site)
The TL431 affords a precise threshold, only turning on once its REF voltage goes above 2.5V (or 1.24V or etc.; many "431" variants are available). It acts like a three-terminal op-amp with open-collector type output and suspiciously large input offset voltage; if the REF input rises above threshold, the output begins to fall, and shortly, current is drawn through the 220 resistors, turning on the 2N4403. This pulls current through the divider, raising V(REF), turning it on faster and harder -- we thus guarantee the SCR isn't left "simmering" but will be turned on soundly when it does. The 100 resistors set gate leakage (pulling down) and peak bias current (pulling up).
Other concerns:
I see a PMOS for reverse polarity protection. Note that your D1 pulls gate voltage below GND, when the input is reversed. Like a BJT's B-E junction, the G-C junction has a low reverse voltage limit, typically 7V or so. This will destroy the SCR, probably the zener, and maybe open the fuse, when much of any reversal occurs.
A rectifier diode (even 1N4148) in anti-series with the zener will suffice to protect against this failure mode. Or for the above circuit, a diode from Crowbar Rail to Sense Rail.
Possible usage notes:
Hot-plugging this circuit, will likely result in transient overshoot, due to the capacitor(s) ringing with the wiring inductance. This can be avoided by using lossy capacitors -- either putting some ESR in series with the 100nFs, or connecting a larger lossy cap in parallel with them. If 5uH is a typical wiring inductance, then \$Z_0 = \sqrt{\frac{L}{C}}\$ is 7Ω, and as much ESR, in series with say 1uF, will suffice. That is, C2 gets an R+C in parallel with it, of these values. (Round to common available values; 4.7 or 6.8Ω would suffice.)
Note also that type 2 ceramic capacitor values vary with applied voltage; choose parts whose characteristic curves indicate less than 30% value loss at maximum operating voltage. For 60V, these will probably be 1206 or larger chip parts, or equivalent size leaded MLCCs. (Type 1 (C0G, etc.) ceramic, film, electrolytic, etc. are not dependent in this way.)
Electrolytic also includes notable ESR, so might be used by itself, assuming other considerations are met.
Also, more likely this circuit is applied at the inlet to a load, a motor driver for example, which itself contains considerable capacitance. In that case, forward R+C damping is not necessary, but it is still necessary for reverse.
You might also want a diode from GND to M1 gate, and from GND to OUT, to rapidly discharge the polarity-protection MOSFET gate during sudden reversal. (Some standards only require handling reversal from a de-energized state; others require tolerance of rapid switchover.)
You might also want EMI filtering, MOV or TVS for load dump or surge protection, etc., depending on application and requirements. Mind that these circuits, as shown, are mere building blocks within a larger input circuit for practical equipment.
