MOSFET gate driver quirk

Question

I Recently started building a SEPIC converter using the TL494 and a BJT-based MOSFET gate drive circuit. When testing the gate drive circuit, I noticed something peculiar. I tested the gate drive circuit in this manner:

And this was the waveform at the gate of the MOSFET (yellow: Vgs; green: Vds):

Needless to say, its hideous. So I did some measurements and came to the conclusion (which I later found was incorrect) that the BJT Q10 was at fault. So I obviously replaced the transistor with what I thought was a 2n3904, but was actually a BS170. The waveform at the gate then became acceptable:

Once I realized that it was a BS170, I replaced it with another 2n3904, but the gate drive voltage was just as bad as it was the first time. I retested the circuit with another 2n3904, but I got the same result. The gate drive circuit worked perfectly with Q10 being the BS170, but not the 2n3904. I'd like to know why.

PS I removed the main MOSFET Q4 and tested the unloaded gate drive circuit with the 2n3904 again, and it spat out a beautiful square wave. When I loaded the driver with a MOSFET, the output collapsed again. It seems that this circuit only works with a small signal MOSFET as Q10 for some reason. Also, an LTspice simulation showed that the gate drive circuit works with the BJT as Q10, but it doesn't on the breadboard!

Answer 1

The BS170 FET can switch 500 mA, with a maximum on-resistance of 5 Ω at 10 V Vgs. It also has a higher input threshold than a 2N3904 BJT which has high hFE as a emitter follower but reduce to 10% of hFE max as a common collector switch which can be as low as 7 Ohms u like the PN2222A which can be 4 Ohms.

But the resonance occurs due to the Ciss of the power FET and low gate resistance during transition which creates an unstable closed loop SCR effect with Q3:Q2 but which reduced current gain of the BJT in Q2 while the FET in Q3’s higher threshold offers some hysteresis and higher gm independent of the load so that Q3’s drain downing low is not bothered Q2’s bootstrapping pulling up the source for the FET in Q3’s source up to Vsup. Thus the FET’s Vgs is adequate for driving the power FET and no oscillation. Thus what I called a hysteresis effect ( of sorts).