RF design stitching vias

Question

Having no past experience on RF design I have recently been taught that placing stitching vias is a good practice. Reading the "definition" of stitching vias I am not sure that I can distinguish stitching vias from common vias. The definition I have read is from Altium:

Via stitching is a technique used to tie together larger copper areas on different layers, in effect creating a strong vertical connection through the board structure, helping maintain a low impedance and short return loops. Via stitching can also be used to tie areas of copper that might otherwise be isolated from their net, to that net.

Is there a difference in functionality between the two types of vias?

--------EDIT---------

Thank you both for the replies. You are very helpful. My design is based on RN2483 package which includes a MCU and a RF IC. If you check RN's bottom layer it is obvious (or I make a guess) where the RF IC is located because there are stitching vias.

On my PCB should I place similar vias?

Here is my current layout:

Now all the vias are connected to GND on top layer. Ignore the one that is overlapping the RFH trace. Now I will add a ground plane to bottom layer as well.

I am open to suggestions/corrections because as I stated it is my first RF design and I lack knowledge.

Answer 1

Perhaps pictures might help. The images below are from a design I recently completed.

The schematic:

This is a RF module designed to operate at around 870MHz, and the schematic shows functional connections, but as this is RF, the layout needs a bit more care:

Although the actual vias are the same size as the rest of them in this area, the ones highlighted by black lines are stitching vias and are not listed as functional connections in the schematic, but are really necessary here.

My rule of thumb for spacing is 1/10 of a rise / fall time for high speed digital and 1/10 of the fastest rate for a sinusoidal signal.

The track to the SMA at the bottom is a co-planar waveguide, where the spacing to the surface plane needs to be maintained, which is why stitching is really a necessity here.

Answer 2

So my question is if there is a difference on functionality between the two types of vias?

No there isn't. If you would ignore all kinds of effects regarding RF, current capability and reliability. Sure, you could use one via to connect one copper area or layer to another layer.

However, this would be a bad idea as one via isn't really a very good and/or solid connection. OK, it is good enough for a signal connection but to properly ground a large copper plate using many vias is preferred. That means "via stitching", similar to how pieces of cloth are stitched together to form clothes, you can use vias to stitch together copper layers.

That gives the advantages of:

• better electrical connection (it can handle more current)
• better thermal connection (better cooling of a chip for example)
• better mechanical connection (instead of just a copper layer, the copper layer now "hooks" into the PCB).
• a lower inductance connection (suppose 1 via is 1 nH, then 10 vias totals to 0.1 nH as they're in parallel, for RF design this is often a must do)
• if one or more vias are broken, it is not a big deal as there are plenty of vias so improved reliability

The disadvantages I see is that the vias will have to be made so that means more drilling for the PCB manufacturer. Also due to lower thermal resistance in some cases soldering might be more difficult as the heat is pulled away more quickly.

But the vias are the same, stitched or not.