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I have designed a high side driven buck-boost converter. When proceeding with the wave forms, I'm getting a considerable amount of ringing in both drain and gate (kindly see the attachments). To avoid the gate ringing I have tried using Zener Clamp Diodes but didn't work. Currently I'm using 47 ohms gate resistor and yet the ringing is there. About the drain ringing I still have no clue on what can be done to avoid it. It would be a huge help if anyone can be of any help. Thanks in advance!

V_DS V_DS

V_GS enter image description here

V_GS Zoomed enter image description here

Schematic Diagram enter image description here

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    \$\begingroup\$ Please edit your question and add (a) a photo showing the oscilloscope probe setup including ground lead, while measuring \$\small\textrm{V}_{GS}\$ ; and (b) the schematic diagram of your design. \$\endgroup\$
    – SamGibson ♦
    Commented Jan 10, 2018 at 5:47
  • \$\begingroup\$ @SamGibson Done \$\endgroup\$
    – Thathsara Radeeka
    Commented Jan 10, 2018 at 6:19

2 Answers 2

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Your probing is awful and high frequency currents in the switching circuits will induce voltages in the loop area formed by your probes. This is what people use when testing circuits like this: -

enter image description here

The spring wire on the earth part of the probe ensures that the loop area you probe is quite small. In other words use a proper oscilloscope probe and a ground spring.

Next, when the MOSFET goes open circuit to interrupt current from the 12 volts into the 33 uH inductor the drain-source capacitance of the MOSFET remains in circuit and this might be several hundred pF. This will form a resonant circuit with the 33 uH inductor and you will get a decaying sine wave at high frequency. This is normal.

It's also normal for the inductor to have a self resonant frequency (due to inter-winding capacitance) that also causes (or adds to) the ringing you might see.

That decaying sine wave can also couple to the gate via the MOSFETs drain-gate capacitance and you can observe a small effect on the gate although I think your biggest problem is probing.

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  • \$\begingroup\$ I agree on the probing technique using some work. It is also generally advised to design switching converters on a two layer board minimum to provide a high frequency return path for the switching currents. Ringing can occur when the return current cannot follow the source current exactly at high frequency. The ringing is the observed travel time that current takes to follow the larger path incurred. Most of the time I would say if you want a quiet switcher you need 4 layers to have a continuous enough plane for those currents to flow. See this. ti.com/lit/an/snva638a/snva638a.pdf \$\endgroup\$
    – Luke Gary
    Commented Jan 11, 2018 at 9:23
  • \$\begingroup\$ @LukeGary good spot about the single-layer PCB - that certainly won't help! \$\endgroup\$
    – Andy aka
    Commented Jan 11, 2018 at 9:25
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You've got 40 nanosecond ringing period, or 25MHz.

The L*C produce (uH * pF) for 25MHz is 40.

If you have 1,000pF Cgate there is 40nanoHenries inductance, or about 2" of wire.

What can you do? To optimally dampen, use R = sqrt( L / C)

Rdamp = sqrt(40nH/1nH) = sqrt(40) = 7 ohms.

Perhaps the ringing path does not include the gate and the gate R.

How about source-drain as the path thru the FET?

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