THe Zout of 7805 is 0.016 Ω @ 1kHz* but since internal feedback gain like an Op Amp reduces with rising f, so does Zout rise with f thus at 10MHz it is out of bandwidth and limits to the load regulation = 100mV/5V=2% @ 1.5A 0.1V/1.5A=67mΩ
Then add any trace inductance and you get...
simulate this circuit – Schematic created using CircuitLab
The location of low impedance ceramic caps affects both what the regulator sees with the Q of the input RLC cct as well as the attenuation of a step C CMOS load dump on the voltage.
Thus as Peter says both locations become necessary for long traces with about 10nH per cm for traces 10:1 length /width up to 30nH/cm for 100:1 ratio as I recall for typical traces. so 50nH is 5cm or 2" for 0.5cm or 5mm wide power traces for 0.035mm thick.
But for power/Gnd planes this reduces to ~ 1nH/via ( depending on L/D ratio) and 2nH/cm for path length for any square plane and thinner dielectric also increases nF/cm^2 with low ESR inverse squared but limited by dielectric breakdown and defects for burrs shorting the supply. Commercial solutions for this exist.
p.s. C2 is the equivalent C for the uC and it also has ESR not shown. C causes dynamic power rise with clock rate. or delta Ic=CdV/dt * delta f. thus C can be estimated. Where dV/dt slew rate is assumed constant but rises with T ['C] thus C becomes the ratio of changes for ΔIc/Δf * 1/ slew rate. ESR is harder and depends on number of FETs switching each about 25 Ohms in parallel.
Thus a final ripple current depends on very low ESR*C =T values <= and >= rise time for load regulation of switched C from Coss of CMOS.
This is my technical analysis of our Rule of thumb to use low C values as close to both the source and the load. as smaller C have lower ESR values limited by smallest size. Tantalum and ultra-low ESR alum e-caps can as low 1us or <1MHz effectiveness, and Ceramic << 1us to <1ns for microwave caps with low ESL.