MOSFET Oscillations when bringing gate to same potential as drain

Question

I was messing around in the lab today looking for a clever way to make a single FET oscillator. I made this circuit, which is basically a high side switch using an n channel mosfet. I have it oscillating but I am not sure if my explanation is correct. If someone could help explain why it is oscillating or prove my theory, I would greatly appreciate that.

As you can see in the second picture, the gate is connected up to the drain which is connected to Vcc. Let's say it is at 10 volts. The source then connects through a load to ground. My explanation is as follows:

1. The fet turns on because the source is pulled down by the resistor to ground and the potential difference between gate and source is > than Vth (2volts).
2. Once the transistor turns on, the drain is now pulled up to Vcc.
3. The gate is no longer 2 volts above the source, because they are both roughly at the same potential.
4. The transistor then turns off because Vgs < Vth
5. Source is then pulled back down to ground.
6. Goes back to step 1.

Does this make sense? Thanks! In the pic below I used 10 volts, you can see that the source comes up to 8 volts (input minus Vth) which makes sense. The oscillation frequency is 360khz and p-p voltage is 0.5v

Answer 1

This looks a classic relaxation oscillator but you can also make a linear oscillator. The Coss , cable inductance (nH) and probe capacitance all may affect frequency.

The Vcc must be above the Vgs for linear operation.

Change to your values like 1k with cable capacitance , inductance and Coss and diode capacitance.

Answer 2

It shouldnt oscillate if there was only a resistance from source to V- and the voltage between V+ and V- was constant DC.

The situation in practice is another. The instruments and the wires to V+ and V- are remarkable inductive and capacitive reactances. In addition I like to see the wire between G and D (where it is when compared to other wires - a possible feedback transformer). If it oscillates, somewhere is enough phase lag (=slowness) that prevents finding the balance. Fet itself has a remarkable capacitanse from G to D and S and the wires increase the effect.

The situation resembles the shower incident. A man in the shower never gets the water to the perfect temperature when he turns it hot, if it's too cold and turns it cold when it's too hot. The slowness is the flow delay.

Please, show us a photo of your circuit. The wire lengths and routes are interesting. The whole case is interesting and is perfect teaching material.

Try, if the oscillation stops when you connect a 10...100 nF capacitor with short wires between V+ and V- as near the fet as possible. Does the frequency vary if you bend and move the wires?