Timeline for recognising patterns in TTL logic analog circuit
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 4 at 12:42 | vote | accept | Chris95 | ||
| Mar 30 at 15:26 | answer | added | Tim Williams | timeline score: 0 | |
| Mar 30 at 14:27 | comment | added | Chris95 | Hello Mr Williams, what is the substructure logic here? | |
| Mar 30 at 11:41 | comment | added | Chris95 | Hello Mr Williams, I think the X means that Vcon is non relevant.Its attached J11 is i think going to be attach to a gate of a mosfet. | |
| Mar 30 at 10:38 | comment | added | Tim Williams |
Could you explain what V_CON is, and what J11-J14 are or what might be attached to them?
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| Mar 30 at 9:42 | comment | added | Chris95 | Hello Mr. Williams, what is the structures you see in here which is combining this circuit?Thanks. | |
| Mar 30 at 8:25 | comment | added | Tim Williams | Looks more like RTL (Resistor-Transistor Logic). Cute, the PNPs are "upside down", but so is the supply; reminiscent of 50s-60s era germanium circuits. | |
| S Mar 30 at 8:10 | review | First questions | |||
| Mar 30 at 12:27 | |||||
| S Mar 30 at 8:10 | history | asked | Chris95 | CC BY-SA 4.0 |