3
$\begingroup$

I have two ADC interfaces with FPGA and 32-bit processed output data from FPGA. I have an IO signals to verify the Inputs and Outputs of FPGA.

But I dont have any test points to verify the intermediate output blocks of the design like mixer and filter. Since I need to cross check the functionality of mixer and filter also either its meeting my requirement or not. What is best method to evaluate the functionality of complete blocks along with intermediate blocks.

Either I am doing right or Is there any best solution to verify the intermediate blocks of design along with actual IOs. Actual blocks of the design is mentioned in the below figure.enter image description here

Improve this question
$\endgroup$
5
  • $\begingroup$ My solution is to give the inputs and verify the outputs as part of FPGA IOs. but taking the intermediate signals as test points in the PCB Board. But adding the test points in the board will consume lot of space for test signals of 32-bit data. $\endgroup$
    – srihari
    Commented Aug 3, 2021 at 13:13
  • $\begingroup$ Can you MUX all the intermediate points out the "32-bit Data" output? That will only increase the I/O count a little for MUX line selection. $\endgroup$
    – Peter K. ♦
    Commented Aug 3, 2021 at 14:44
  • $\begingroup$ Looks like this approach will meet my requirement, But in general, I am not sure how a signal processing processing design is verified in simulation and Board Testing. $\endgroup$
    – srihari
    Commented Aug 3, 2021 at 16:30
  • $\begingroup$ Since I dont have any idea on FPGA output samples for a given specific ADC Input samples $\endgroup$
    – srihari
    Commented Aug 3, 2021 at 16:40
  • $\begingroup$ You have a 16 bits ADC and need 32 bits of data at the output of the filter, isn't this too much? $\endgroup$
    – user51024
    Commented Aug 3, 2021 at 19:07

1 Answer 1

Reset to default
1
$\begingroup$

I suppose you're using either a Xilinx or an Intel FPGA. Xilinx has Chipscope and Altera has SignalTap. You can use these tools to spy inside your FPGA. Here's what I would do :

1 - Setup SignalTap to retrieve your ADC output (that is the input to the mixer), the 8-bit mixer inputs and the mixer outputs.
2 - Adjust the data width of SignalTap so that you capture a significant number of samples.
3 - Retrieve the data with SignalTap.
4 - Analyze the data in Matlab/Octave/Python and validate your implementation.

However, you should have designed a testbench to validate your code prior to the FPGA implementation. It is much faster to catch a bug in simulation than it is to catch it in the field.

Improve this answer
$\endgroup$
4
  • $\begingroup$ This approach will not produce any evidence for design under Test. Where as the mentioned approach will provide debug facility but will not provide any evidence for capturing the results along with actual outputs and intermediate outputs. $\endgroup$
    – srihari
    Commented Aug 3, 2021 at 16:24
  • 1
    $\begingroup$ Why not? Compare what you capture with SignalTap against your Matlab model $\endgroup$
    – Ben
    Commented Aug 3, 2021 at 16:47
  • $\begingroup$ If I have a 40K samples its very difficult to fed either in simulation or On-board testing. $\endgroup$
    – srihari
    Commented Aug 3, 2021 at 17:10
  • 1
    $\begingroup$ Of course, you can only test a subset of these samples. That being said, you could probably grab something like 4096 or 8192 samples which might help you debug your processing chain. $\endgroup$
    – Ben
    Commented Aug 3, 2021 at 17:11

Not the answer you're looking for? Browse other questions tagged or ask your own question.