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I was reading the paper about the first M87 EHT Results, part 3 (link to article PDF), where the data processing pipeline is explained. The recording system used was a Mark 6 recorder with 32Gbps and 2 bit sampling. Why is the quantization so coarse? I think I am missing something since the measurements have a very large dynamic range. Can anyone explain what this 2 bit sampling means?

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  • $\begingroup$ Sounds like it 4-level (2 bits) of quantization sampled at 16 gigasamples per second (32 Gbps / 2 bits per samples). High speed analog to digital converters usually have a coarse resolution. I don't have a reference to the design, or I'd use this as part of an answer. $\endgroup$ Commented Oct 10, 2022 at 20:39
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    $\begingroup$ Homepage for Mark 6 VLBI data recording system - may be too far down into the hardware/computing weeds... $\endgroup$ Commented Oct 10, 2022 at 22:37
  • $\begingroup$ Different but related: Why are the ALMA receivers' ADCs only 3-bits? There are four answer posts there, but I still don't really understand why. I assume that there is mathematical magic that shows that for some bandwidth limit one can recover the full signal by oversampling in speed while under-sampling in resolution, but I don't know what that is yet. I'm sure that's the easier option for the hardware designer; nobody want's to make a 24-bit 2 GHz ADC with ultra-low differential nonlinearity if they don't have to. $\endgroup$
    – uhoh
    Commented Oct 10, 2022 at 22:57

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