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I am reading a book that is describing the roles of the NB and SB (North Bridge and South Bridge) and the book explains the roles of each one. However, I'm wondering, is the SB capable of supporting PCIe communication? This question came to mind because I've seen a few pictures that show the SB supporting PCIe on a few different websites, so I wanted to be sure.

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Yes, the southbridge is capable of supporting PCIe in some cases, but in maximum cases it is supported by the northbridge.

I used to own an Asus motherboard (P5GZ-MX) based on the Intel 945GZ + ICH7 chipset. The board supported PCIe via the Southbridge Intel ICH 7 (I/O Controller Hub) as the Northbridge 945GZ Express chipset did not support PCI Express. The board could support PCIe cards up to 4× mode max.

To validate the above statement I am giving a little extract from the motherboard’s manual.

The Intel ICH7 Southbridge represents the seventh generation I/O controller hub that provides the interface for PCI Express and high definition audio.

But today’s architectures do not have the concept of northbridge and southbridge any more. Now a days most of the northbridge components the iGPU, Memory Controller and PCIe Controllers are integrated into to the CPU itself. Other than the CPU, a single chipset called the PCH (Platform Controller Hub) usually handles all the other I/O devices of the motherboard, and is directly connected with the CPU. The PCH may support additional PCIe lanes, but the main PCIe lanes are supported by the CPU, in which we usually install the GPUs or the demanding I/O devices. The additional PCIe lanes from the PCH are usually utilised for some less demanding I/O devices like sound cards, USB 3.0 expansion cards, etc.

A block diagram of the old northbridge-southbridge architecture.

A block diagram of the current system architecture.

One point to be noted is that Intel uses the term PCH, while AMD calls this chipset the Fusion Controller Hub (FCH). Their functions are more or less the same.

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  • It should be noted that the connection between the io hub (SB) and the PCH or CPU may be bandwidth limited Commented May 7, 2015 at 8:47
  • bandwidth numbers for the hubs: superuser.com/a/692550/250180 Commented May 7, 2015 at 8:59
  • I was researching PCH, this is superb, thanks for sharing this. And i think ill bolden up that FCH a bit, almost missed it, and its crucial info. Im steering away from AMD nowadays, finally, as one of the last holdouts, myself. Commented Dec 6, 2016 at 22:28

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