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What books and articles can you recommend to learn basis of cache coherence problems in big SMP systems (which are NUMA and ccNUMA really) with >=16 cpu sockets?
Something like SGI Altix architecture analysis may be interesting.
What protocols (MOESI, smth else) can scale up well?
I would have a look through docs.sun.com for documentation for the UltraSPARC CPU as well as some of their bigger systems. They've been dealing with issues like this for a long, long time, and their documentation is usually excellent.
@osgx: More accurate links will depend on exactly what sort of questions you have. Your best bet is to spend some time looking through their documentation and finding exactly which aspect interests you most, then drilling down further into that specifically.