Firstly, now with on-CPU memory controllers this is much more irrelevant, the CPU is now connected directly to the memory and so the FSB -> Northbridge -> Memory frequencies matter much less as the CPU memory controller frequency is the same as the memory frequency.
Typically though there would be a small buffer for memory requests on the northbridge, but also there are control lines between the CPU and northbridge (or more recently between the CPU and memory) that are "Data Ready" lines that signify when data had been fetched by the northbridge and is now ready to be transferred to the CPU. These types of control lines are similar to a modem that uses a RTS/CTS (Ready-To-Send/Clear-To-Send) mechanism to signify that data is ready and that the receiver is ready for it to be sent.
Because of these control lines and small buffers the actual frequencies of each link between various components can be different. The memory and controller can support one speed, then the northbridge forwards on the data to the CPU at a different speed.