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I have an AMD 5800x, which has 20 pcie 4.0 lanes.

I want to put 2 GPUs (both support pcie 4.0) in a motherboard with 2 PCIe x16 slots, but 1 of them is version 4, and another is version 3.

4 lanes are used for SSD. The rest is 16 lines, they will be split 8+8 between cards.

So my question is, since the second card is in the pcie3, will it work at 16 lines (which is speedwise equivalent to 8 lines of pcie4), or there will be 8 pcie3 lines?

In other words: what is splitted during splitting: lines or total speed? Is there a "conversion" of 8 pcie4 lines into 16 pcie3 lines?

If not, it makes more sence to split a x16 pcie4 slot into 2x8 slots, and not use pcie3 x16 at all?

Update. Chipset is B550

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    How many PCIe lanes does the CPU provide?
    – Ramhound
    Commented May 25, 2023 at 11:27
  • Most likely one slot is from the CPU while the other slot is provided by the motherboard chipset which communicates with the CPU over a different interface.
    – Mokubai
    Commented May 25, 2023 at 11:29
  • It is written in the first sentence: CPU has 20 pcie lines
    – DDR
    Commented May 25, 2023 at 13:00

2 Answers 2

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In modern systems one of the PCIe slots is provided by the CPU, usually the fastest and widest slot, while the rest are provided by the platform chipset.

From Anandtech: AMD Zen 4 Review there is a general block diagram showing the platform.

enter image description here

On the left you see in the center block that it has a load of PCIe lanes allocated to the GPU, NVMe and Chipset Downlink, then on the right the Chipset Downlink connects lanes to other slots and peripherals.

Obviously this will mean sharing bandwidth and other performance issues compared to the slots directly connected to the CPU, but this will likely be true of almost every motherboard regardless of whether the system is AMD or Intel.

This is also representative of a newer system, but is generally applicable to almost any motherboard manufactured in the last 10 years.

Some motherboards might actually have two slots split from a single x16 bus, per this image from ServeTheHome

enter image description here

Notice the multiplexer on the second slot in the top left. It allows the first slot to have 16 lanes if nothing is in the second slot, or both slots to have 8 lanes if there is something in the second slot.

You will need to consult your motherboard manual to know more precisely what each slot will support and it should indicate which are shared or split performance slots.

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    The bottom line is the manual for the motherboard will outline how each slot will interact with other slots when they are used and unused. My suggestion would be to look at manual to determine what mode each slot will run at.
    – Ramhound
    Commented May 25, 2023 at 11:54
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This is impossible to answer "as is".

This is implementation dependent. There is no generally applicable answer.

It totally depends on the motherboard and the Bios/UEFI implementation in combination with the GFX cards and any other attached hardware that needs CPIe lanes (like M.2 SSD's).

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