Why RISC-V must get its messaging right on open standard vs open source

Feature The possibility of America placing sanctions on RISC-V has increased the pressure on RV's governing body and its partners to get their messaging right about what this technology really is.

One of the primary tools of the US and China in their trade war is placing sanctions against each other. The United States and its allies have prevented China from importing certain advanced processors, tools for making chips, and intellectual property for chipmaking and AI. In retaliation, China has banned certain Western-made semiconductors from the country, and has been supporting efforts to make everything it needs in the Middle Kingdom itself.

The open source characterization [of RISC-V] was natural but frankly a mistake

RISC-V International – which oversees the open, royalty-free CPU instruction set architecture RISC-V – has been caught in the middle of this international squabbling. RV is used all across the world, including in America and China. Various US politicians from both the Republican and Democratic parties have voiced their concerns that the open nature of RISC-V allows Chinese companies to take American technology and bypass sanctions.

The RISC-V community would rather not have its instruction set architecture (ISA) hit with export or import sanctions, as that would affect adoption and encourage fragmentation. It hopes to avoid a crackdown by getting lawmakers, policy wonks, and officials to understand what the community sees as the subtle difference between open source and an open specification.

Simply put, they hope to press the point that it's one thing to hit a product with trade restrictions – say, a particular computer processor, or a paid-for software application, or even an open source project – but quite another to hit an open standard or specification with restrictions. It's the difference between banning, for example, exports of certain Ethernet network controllers, and straight up banning the export of Ethernet as a whole.

In the eyes of the RISC-V world, the latter – if applied to RISC-V – would be unfair overkill. It would be a blanket ban on all RISC-V-compatible processors rather than just those specifically chosen by a government on, say, national security grounds. As such, the community is hoping to educate everyone on the distinction between open source and open royalty-free specifications. RISC-V is a free and open specification, but that doesn't mean all RISC-V-compatible processors are open and freely available for China to take.

Haunted by an open source ghost

Software – be it applications, operating systems, you name it – is ultimately made up of instructions that tell the hardware what to do. A program might look up a value in memory, and if it's zero, take some action – each of these steps is typically an instruction for the processor to carry out. As an ISA, RISC-V describes the format and operation of these instructions on RISC-V processors. That way it should be possible to build programs for RISC-V that run on any and all compatible RISC-V chips.

All RISC-V does is specify what software should expect of a RISC-V processor – it is up to processor designers to decide how exactly they implement that specification. RISC-V is open and royalty free to use, but the chips themselves can be either open source designs or closed and proprietary. The RISC-V world fears it will be broadly hit with sanctions if it can't get officials to see that distinction.

That's not to say all those in public life are too dumb to understand. Anyone vaguely familiar with RISC-V may be confused that the official position of RISC-V International today is that its ISA is an open specification and explicitly not open source. But plenty of people since the birth of RISC-V in 2010 have called it open source – including RISC-V chip designers and other champions of the spec.

The ISA is not described as open source by Krste Asanović and David Patterson, who helped steer the architecture's genesis, in their 2014 paper, "The case for RISC-V." That paper [PDF], which outlines the reasons why RISC-V would be good for the chip industry, almost exclusively refers to the ISA as simply "open" – rarely using either "source" "standard."

Early on in RISC-V's life, calling it open source wasn't really a problem, former RISC-V International CTO Mark Himelstein told The Register. The project, which originated in the Parallel Computing Laboratory at the University of California, Berkeley, was often compared to the open source operating system kernel, Linux. A great many initial RISC-V CPU designs were open source. At the time the RISC-V world was okay with that association with Linux, allowing it to ride the coattails of the kernel. And this idea that being open hardware meant no secrets, no proprietary lock-in, and no big bills for licensing and royalties.

Though seemingly innocuous, draping RISC-V in the open source banner resulted in unforeseen consequences.

"The open source characterization [of RISC-V] was natural but frankly a mistake," Himelstein lamented in hindsight. Once RISC-V began to mature and appeared in commercial applications, calling it open source no longer made sense. Engineering houses such as SiFive took the open RISC-V ISA and created non-open-source implementations of it in CPU cores for various chips.

We have made a concerted effort to update our terminology for greater clarity and consistency in our work as a standards body

"Our community thrives on the open collaboration, numerous contributions, and invested resources of our community," RISC-V International CEO Calista Redmond told The Register. "In this regard there are many similarities between how we cultivate our resulting technical deliverables and how the open source software community works. 

"Due to this, the terms 'open source' and 'standards' were often used interchangeably. We realized this was causing confusion as there are nuances between standards and open source software. Hence, we have made a concerted effort to update our terminology for greater clarity and consistency in our work as a standards body."

That effort to position RISC-V more clearly as an open specification rather than open source hardware came about some time in late 2022 and early 2023. The phrase "open standard" was put front and center, and Himelstein explained as much in May 2023 outlining the differences between open source and open standard – stating that RISC-V was definitely the latter. Its implementations can be either open source or commercial and closed, but the ISA itself is a collection of ratified documentation.

It didn't take long for RISC-V International to pivot from clearing up confusion to battling a potential US ban on the architecture's export.

Not a national security risk nor sanctionable, says RISC-V firms

The initial push for sanctions on RISC-V came in the latter half of 2023, when Republican and Democrat members of Congress voiced their concerns in a letter [PDF] to commerce secretary Gina Raimondo about the ISA being a gateway for China and other rival countries to get their hands on US technology.

"RISC-V is an open source technology instruction set used for the development of custom processors," the memo read. "RISC-V allows the People's Republic of China (PRC) to use open source architecture to develop advanced chips without needing a license from the US government. For example, leading PRC AI firm Biren is on the Department of Commerce's Entity List and is reportedly working with RISC-V technology."

RISC-V advocates protest this characterization of the ISA as "open source" – it isn't a distinct technology to ban, in their eyes. The Register spoke to RISC-V International and outfits that design their own RV-compatible processors, and they pretty much all argued that sanctions wouldn't merely be disruptive and terrible publicity, they'd be more or less impossible to enforce.

"Sanctioning RISC-V gets unimaginable pretty fast," explained SiFive senior vice president Jack Kang. Since RISC-V is an open standard that is already well documented in public, it would be impossible to ban it effectively and prevent China from using the architecture. It would basically be like a ban on Wi-Fi or PCIe – an analogy many in the community have used, including RISC-V International boss Calista Redmond.

What's more, the RISC in RISC-V stands for Reduced Instruction Set Computer; by its very nature, RISC-V is a small ISA. It has a base specification of no more than about 50 instructions, with optional extensions that bring in more instruction types. This is far less than what's set out by rival x86 and Arm specifications. RV isn't a sprawling architecture or a crucial blueprint for Beijing to exploit freely, so there isn't a whole lot to ban – or so the argument goes. All the magic and technology is below the ISA, in the individual CPU core implementations – some of which are open source, and some not.

"The amount of information published about RISC-V is less than that which is published about Arm and x86," Kang observed.

Another facet to this is that RISC-V International is based in Switzerland, while a lot of RV CPU design work is done in the US or within reach of Uncle Sam. It would be interesting, to say the at least, to see how export controls on the ISA might work in that context.

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And though many RISC-V CPU cores were open source in the beginning, it's not in the interests of RISC-V outfits to make their designs open source, since that would allow competitors – including those in China – to use them for free. So although the ISA remains open, implementations are increasingly closed.

"SiFive's products are not open source," Kang noted. Virtually all open source RISC-V CPUs were designed by researchers and academics, but there's very little incentive for a business like SiFive to open source a core that's commercially competitive.

Andes Technology, another RISC-V chip designer, concurred. "RISC-V is more of an idea that everyone riffs off of," an Andes representative told The Register.

Undoubtedly, the existence of RISC-V does give Chinese chip designers a good starting point on processor development as well as a software ecosystem. Linux, various toolchains, and other code has been ported to the ISA. But those designers are on their own if they want to pursue AI and high-performance computing.

"Distinguishing between 'open standard' and 'open source' architecture is not a preference in vernacular," SiFive argued. "There are fundamental differences between these terms that dictate how ISAs are designed, used and protected."

That's not even mentioning the fact that China struggles to produce advanced chips (usually defined as using a smaller than 10nm process node) at scale, and will probably struggle to do so for years to come.

It's difficult to get politicians to listen, but it's not risky at the moment

Communicating these points to politicians to get them to back down from potential sanctions has been difficult.

Part of the problem is that the topic is fairly technical. At a glance, the difference between open source and open standard may seem pretty minor, and the years of saying RISC-V is completely open and free without nuance didn't help.

But there may be more to it than just basic confusion. In January, the New York Times reported that Arm was lobbying politicians for restrictions on RISC-V.

Arm sees RISC-V as a significant rival, and the feeling is mutual. RISC-V International likes to point out the licensing fees associated with using Arm technologies, and the restrictions Arm places on the tweaking of its tech. Those in the RISC-V camp see Arm as expensive and inflexible, while the Arm world sees RISC-V as fragmented, too flexible, and lagging in terms of design and performance.

None of the individuals The Register spoke to in the RISC-V industry could say with certainty that Arm was whispering in the ears of policymakers – but they all suspected that was the case.

The idea of the US sanctioning RISC-V in some way is ludicrous, but if it happened it would probably hurt the States more than some would think. It would disrupt businesses that provide competition to the likes of Arm and Intel, which leaves system-on-chip designers and users worse off, while China continues to use the ISA. Private enterprises such as SiFive would be disadvantaged – but so would NASA, which is a SiFive customer.

"If people aren't understanding the distinction, poor policy decisions can be made with huge unintended consequences, practical or not," Kang argued.

One of the greatest safeguards that could stave off sanctions is RISC-V increasing its popularity and usage. "The only thing we can do is make RISC-V bigger every year," an Andes spokesperson suggested. "The bigger it is, the harder it is to sanction."

Without sanctions to keep it down, RISC-V is expected to expand in the coming years. Analysis firm Omdia predicted AI and automotive sectors will drive adoption of RISC-V chips, and estimates nearly 600 million AI-accelerating RV-compatible CPU cores will be produced annually by 2030. In total, it reckons 17 billion RISC-V chips of all sorts will ship in 2030.

RISC-V is not exactly fighting for its life, yet. Neither RISC-V International nor orgs using the ISA are too concerned about proposed sanctions coming through – at least not under the Biden administration. And although commerce secretary Raimondo is now looking into the sanctions suggested in the bipartisan letter from last year, Kang doesn't think it's an indication that any action will be taken.

"The recent letter from the Department of Commerce takes the right approach, and SiFive is in support of this re-examination," he opined, referring to this letter from the Dept of Commerce to lawmakers promising a review of possible action.

The messaging issue surrounding RISC-V will probably persist for a while longer – especially as it gains in popularity, in both the US and China. The situation isn't critical, but sticking to a consistent message in the long term will be necessary to keep it that way. ®