Intel's quantum leap in wafer-wide cryo-testing sets cool new standard

Intel says it has made two advancements towards realizing silicon-based quantum processors which involves optimizing a standard fabrication process and developing a means to test the quality of resulting individual devices across a full 300mm wafer.

The Santa Clara chipmaker has labored for some time towards spin qubit technology for quantum computers that can be mass produced using the same semiconductor manufacturing processes used to churn out its classic processor chips.

In a research paper published in Nature, the Silicon Valley biz set out the latest advances intended to move the company a step closer to its ultimate goal of powering fault-tolerant quantum computers the same way its chips have powered PCs over the past several decades.

Intel says the advances were made possible through the use of a cryogenic wafer prober (aka cryoprober) - a cryogenic chamber large enough to hold an entire silicon wafer for testing purposes, first demonstrated in October 2022. This has enabled it to perform "novel statistical characterization" of its silicon qubit devices, and make iterative improvements to the yield, uniformity, and fidelity of the devices it can produce.

Full-wafer probing is standard for testing in the semiconductor industry, but the need to cool most quantum devices down to cryogenic temperatures had previously meant these were typically tested one at a time.

Spin qubit arrays have reached a handful quantum dots, Intel says, but for practical quantum applications, the physical qubit count will need to be increased substantially. This calls for fabrication techniques to deliver spin qubit devices with a density, volume, and uniformity comparable to current processor chips that contain billions of transistors.

This is because Intel's quantum dot technology is based on single electron transistors, the company previously told us. A single electron is trapped under the transistor gate, and its quantum property called spin is used to represent the qubit.

Intel's paper, Probing single electrons across 300mm spin qubit wafers, details what the chipmaker calls an optimized industry-compatible process to fabricate spin qubit devices on silicon/germanium (Si/SiGe) heterostructures (substrates), plus a cryogenic probing process to collect high volumes of data on the spin qubit devices across an entire 300mm semiconductor wafer.

"Cryogenic" here means that the entire wafer has to be cooled close to absolute zero to measure the characteristics of the qubit devices, and only recently has wafer probing at such low temperatures become possible, Intel notes.

The spin qubit devices Intel researchers tested for this paper were fabricated in Intel's D-1 R&D fabrication plant in Oregon, where the company's CMOS logic processes are developed. The host material was a silicon/germanium (Si/SiGe) substrate grown on 300mm silicon wafers.

According to the paper, the patterning for the quantum dot gates was done in a single pass with extreme ultraviolet (EUV) lithography, allowing the researchers to explore gate pitches from 50nm to 100nm.

To achieve high yield, a combination of processes from industrial transistor manufacturing have been adopted. The quantum dots are defined by a planar architecture, where the gates used for controlled accumulation are defined in one layer, while the gate electrodes are isolated from the substrate by a high-dielectric-constant composite stack, or "high-κ stack" and neighboring gates are isolated from each other by a "spacer" stack.

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One key approach for improving device variation and performance that Intel details in the paper is to reduce fixed charge in its high-κ stack, and optimize the gate layer architecture. The fixed charge can be reduced by limiting the temperature of the spacer process during deposition, leading to reduced crystallization of the high-κ stack at lower temperatures, the company claims.

After optimization, Intel researchers then characterized the fabrication process with measurements on 12-quantum-dot (12QD) devices created with a 60nm gate pitch. These consist of a linear array of a dozen quantum dots with four opposing sensor dots isolated by a center screening gate.

These are possibly similar to the Tunnel Falls 12-qubit test chip Intel has handed to research laboratories for experimentation since last year.

The array of quantum dots can be operated as physical qubits in a variety of spin encodings, including single spin qubits or exchange-only qubits (in a four-qubit array). Depending on the spin qubit encoding, an optional micromagnet layer can be added to the device and the center screening gate can supply microwave electric fields to control the qubits with electric dipole spin resonance, according to the paper.

To analyze the yield of this fabrication process, Intel says it tests 232 12QD devices across a wafer, calculating the component yield for ohmic contacts, gates, quantum dots and full 12QD devices.

The cryoprober used was manufactured by cryogenics company Bluefors and wafer level test outfit AEM Afore, but was developed with Intel, says the chipmaker. It can load and cool 300mm wafers to a base temperature of 1.0 K in around two hours.

When testing, an individual device is aligned to the probe pins using the wafer stage control and a machine vision algorithm. The wafer is brought into contact with the probe pins to electrically connect it with voltage sources and current and voltage detectors at room temperature.

In the example given in the paper, the chipmaker says that a large number of gates (>10,000) were tested and found to be working on the wafer in question, and claims this demonstrates the consistency of its gate fabrication process.

Quantum dot yield was estimated to be 99.8 percent, and the full device yield, including the linear array of 12 quantum dots and the four charge sensors, was claimed to be 96 percent.

Intel paper concludes that the high device yield it is able to achieve, combined with cryoprober testing, makes it easier for Intel to study its spin qubits in order to improve them, eliminating failures owing to yield or electrostatics at the dilution refrigerator stage.

"High-volume testing with the cryoprober will continue to enable process optimization to reduce variation and disorder, as well as more advanced performance screening to identify the leading-edge test chips for quantum computing applications," the paper's authors say.

"Altogether, these results set a new standard for the scale and reliability of spin qubit devices today and pave the way for much larger and more complex spin qubit arrays of the future."

The paper shies away from forecasting when Intel might be able to produce enough spin qubit silicon to make a reliable quantum processor possible. However, the chipmaker told us previously that quantum technologies with the scale and reliability to have an impact won't arrive "until well after 2030." ®