Samsung Semiconductor’s Post

13 of 14 #job #openings on 3/14 ✴️ Model and system Co-design, #gpu efficiency for #ai training ✴️ LinkedIn As promised, I am #sharing today for #piday: ✅ 3 #intern #roles ✅ 14 #job #opportunities ✅ 9 #postdoc and #phd #positions #checkitout and #share #follow me Suresh V. for more of such #information #opportunity #usajobs #usa #hiring #hiringnow #open #jobsearch #reshare #engineeringjobs #engineering #givingback #spreadtheword #connectandgrow #repost

I have worked on all levels of DFT positions for over 2 years now and I have learned that it is one of the most sought after and extravagant positions in the hardware industry... So, please enjoy this very elegant poem from Chatgpt to let you know I am working on hiring two Principal/Lead DFT Engineers with two of our most exciting companies working on processors for LLMs and unseen interconnect architectures. Please enjoy or don't, but at least reach out if you are interested or know someone who is. And keep DFTting. In circuits vast, where currents dance with grace, A DFT engineer finds their sacred space. They delve into realms where signals roam, Navigating the labyrinth of silicon home. With algorithms sharp and tools refined, They seek the flaws the eye's blind. In the realm of digital, where bits take flight, They sculpt precision from the chaos of night. Through gates and registers, they weave their art, Unraveling mysteries, playing their part. Each test a quest, a journey deep, To awaken the secrets that circuits keep. They wield the language of ones and zeros, Crafting solutions with meticulous zeros. In the symphony of circuits, they find their song, Harmonizing with logic, where they belong. With a steady hand and a brilliant mind, They tame the wild, leaving no fault behind. For in the world of DFT, where challenges gleam, They are the architects of the digital dream. #hiring #DFT #Designfortest #LLMs #bottlenecks #datacenter #Artificialintelligence #AI #interconnects #highspeedIO #semiconductorhiring #aihardware

We're hiring an #Embedded Engineer! Join us at Ambient Scientific and contribute to pioneering AI CPU technology. Apply now at Ambient Scientific Careers to shape the future of embedded systems. EmbeddedSystems #AI #CPUDesign #FirmwareEngineering #EmbeddedSoftware #EngineeringJobs #CProgramming #ARM #MCUPeripherals #SoftwareTesting #ContinuousIntegration #Git #PythonScripting #Leadership #ProjectManagement #JIRA #TechJobs #HiringNow

My post about hiring Software Engineers (C, C++, C#) has seen over 500 visitors. #computervision. We want people who can learn... we found multiple errors in the algorithms and are rewriting the whole thing in order to optimize. Bias sources were found in calibration, Bayer pattern interpolation, compression, telemetry, fusion... which causes poor performances in SLAM, AI, 3D vision, even cybersickness... The main gig is about computer vision, numerical methods, non linear programming, real time embedded systems, digital control, metrology... We will start porting our optimized methods in FPGA ...

Hi All, I'm currently #hiring for an Algorithm Engineer (C++/C/ML). Please click on the job title below to view the Job Description and apply to it! #DL #ML #machinelearning #algorithm #sgjobs #worknow #pytorch #tensorflow #mlflow #AI

Opportunity

🚀 Achieving Design Excellence: The Goal of Synthesis Stage with Fusion Compiler! 🌟 As digital design engineers, we understand that the synthesis stage plays a pivotal role in shaping the success of our designs. With tools like Fusion Compiler, the goal is clear: to transform high-level design descriptions into optimized, efficient hardware implementations. Here’s why the synthesis stage using Fusion Compiler is essential: ### 🎯 Optimizing Design for Performance and Efficiency At its core, the synthesis stage aims to: - **Translate RTL to Gates**: Converting Register Transfer Level (RTL) descriptions into gate-level netlists that are optimized for performance metrics such as speed, area, and power. - **Applying Design Constraints**: Implementing timing, area, and power constraints to ensure the final design meets functional and performance specifications. ### ⏱️ Accelerating Time-to-Market Fusion Compiler facilitates: - **Faster Design Closure**: Streamlining the path from design entry to final netlist, reducing iteration cycles and accelerating time-to-market for complex designs. - **Predictable Design Outcomes**: Ensuring predictable design behaviors across different operational conditions through rigorous timing analysis and optimization. ### 🛠️ Leveraging Advanced Automation With Fusion Compiler, engineers benefit from: - **Automated Optimization**: Leveraging sophisticated algorithms to automate design optimizations, enhancing efficiency and minimizing manual effort. - **Integrated Design Flows**: Seamlessly integrating with other EDA tools to provide a cohesive design flow from synthesis through to physical implementation. ### 🔍 Ensuring Design Integrity Maintaining: - **Timing Closure**: Achieving timing closure by optimizing critical paths and ensuring signals arrive at their destinations within specified clock cycles. - **Functional Verification**: Validating design functionality throughout the synthesis process to guarantee correct operation under diverse scenarios. ### 🌐 Enabling Collaboration and Innovation Fusion Compiler fosters: - **Collaborative Design Environments**: Facilitating communication among design, verification, and implementation teams, promoting synergy and efficiency. - **Innovation Drive**: Empowering engineers to push the boundaries of digital design, creating solutions that meet evolving industry challenges and customer demands. By harnessing the capabilities of Fusion Compiler at the synthesis stage, we empower ourselves to deliver optimized, high-performance designs that not only meet but exceed expectations in today's competitive marketplace. #digitaldesign #fusioncompiler #synthesis #semiconductor #EDA #vlsi #engineeringexcellence #innovation #workwithuppula Thanks, Vishnu DM || Follow Vishnu Uppula for more learning in semi-conductor industry.

𝐃𝐞𝐚𝐫 𝐂𝐨𝐧𝐧𝐞𝐜𝐭𝐢𝐨𝐧𝐬 I'm delighted to introduce two accomplished researchers from MERL – Muhammad Shameel Ansari and Ameen Raza Khan . Both have consistently impressed with their technical expertise, dedication, and valuable contributions to our team, particularly in the realm of hardware design and verification. 𝐌𝐮𝐡𝐚𝐦𝐦𝐚𝐝 𝐒𝐡𝐚𝐦𝐞𝐞𝐥 𝐀𝐧𝐬𝐚𝐫𝐢 brings a powerful combination of hardware design and verification skills. His achievements include: Verification Excellence: Played a crucial role in developing a robust verification environment for the AI-FPU, ensuring its accuracy and reliability. Enhanced Usability: Created an intuitive and user-friendly graphical interface for the AI-FPU, significantly improving its accessibility. Peripheral Expertise: Successfully designed and verified the GPIO and PWM peripheral IPs, contributing to the overall functionality and performance of MERL projects. FPGA Proficiency: Utilized his expertise in FPGA emulation to provide a reliable platform for testing and validation of these components. Backend Development: Contributed to the backend development of the Liberty Analyzer, leveraging Python skills to enhance the tool's functionality and efficiency. 𝐀𝐦𝐞𝐞𝐧 𝐑𝐚𝐳𝐚 𝐊𝐡𝐚𝐧 demonstrates exceptional proficiency in PY-UVM methodologies and hardware design. His expertise is evident in: PY-UVM Frameworks: Designed Python-based UVM frameworks for the RISC-V Single Cycle Core and the SweRV EL2 Core, significantly enhancing MERL's verification capabilities and project efficiency. Verification Prowess: Developed a PY-UVM framework for the Timer Peripheral, showcasing his strong grasp of verification methodologies. Peripheral Design and Verification: Successfully designed and verified the I2C Peripheral, ensuring its seamless integration and optimal performance within MERL systems. FPGA Expertise: Played a crucial role in the FPGA emulation of both the Timer and I2C Peripherals, providing reliable platforms for testing and validation. Backend Development: Contributed to the backend development of the Liberty Analyzer, leveraging Python skills to enhance the tool's functionality and efficiency. Beyond Technical Expertise Both Muhammad and Ameen have actively fostered a skilled team by serving as trainers in RISC-V based training sessions. Their professionalism, dedication, and ability to tackle complex challenges have earned them high regard from colleagues and supervisors. Seeking New Opportunities? If your organization is searching for talented individuals with expertise in hardware design, verification, Python, and RISC-V, I encourage you to connect with Muhammad Shameel and Ameen in the comments section below. They are eager to explore potential opportunities that align with their skills and experience. #MERL #HardwareDesign #HardwareVerification #RISC-V #Python #Talent P.S. Sharing this post can help connect these valuable researchers with the right opportunities!

🚀 Unlocking Enhanced Efficiency with fxCompileStages in Fusion Compiler! 🛠️ Excited to explore **fxCompileStages**, an innovative capability within Fusion Compiler that transforms the synthesis stage of digital designs. Here’s why fxCompileStages is a game-changer: ### 🌟 Streamlined Synthesis Process fxCompileStages optimizes the synthesis flow by: - **Automated Stage Management**: Intelligently managing synthesis stages to enhance design efficiency and performance. - **Sequential Optimization**: Sequencing tasks to ensure optimal resource utilization and faster design closure. ### ⏱️ Accelerating Time-to-Market Contributing to faster design closure and validation: - **Reduced Iteration Cycles**: Minimizing the number of synthesis iterations required, accelerating time-to-market for complex designs. - **Enhanced Predictability**: Ensuring predictable design behaviors and outcomes across different operational scenarios. ### 🛠️ Advanced Design Automation Leveraging automation to simplify design complexities: - **Integrated Optimization**: Automating optimizations across multiple stages of synthesis, from RTL to gate-level netlists. - **Tool Integration**: Seamlessly integrating with other EDA tools to streamline the entire design flow. ### 🔍 Ensuring Design Integrity Maintaining timing and functional correctness: - **Timing-Aware Synthesis**: Optimizing design timing constraints at each stage to meet performance targets without compromising quality. - **Functional Verification**: Validating design functionality throughout synthesis stages to ensure robustness and reliability. ### 🌐 Facilitating Collaboration Enhancing collaboration among design teams: - **Cross-Functional Coordination**: Facilitating communication between synthesis, verification, and implementation teams for cohesive project execution. - **Team Efficiency**: Improving efficiency in multi-disciplinary design environments with synchronized workflow management. ### 🚀 Driving Innovation in Digital Design By leveraging fxCompileStages in Fusion Compiler, designers can achieve: - **Optimized Design Performance**: Enhancing design efficiency and performance metrics through streamlined synthesis methodologies. - **Scalable Solutions**: Providing scalable synthesis solutions that adapt to evolving design requirements and industry standards. Harnessing the power of fxCompileStages underscores Fusion Compiler’s commitment to advancing digital design capabilities, empowering engineers to create high-performance, reliable designs that meet the demands of today’s technology landscape. #digitaldesign #fxcompilestages #fusioncompiler #synthesis #semiconductor #EDA #VLSI #techInnovation #workwithuppula Thanks, Vishnu DM || Follow Vishnu Uppula for more learning in semi-conductor industry.

Quantum computing is entering an exciting new stage, sometimes dubbed "early fault-tolerance", where quantum error correction (QEC) nears the break-even point. This means that logical qubits - which encode quantum information redundantly over many physical qubits - achieve reliability comparable to that of the underlying physical qubits. This essentially fires up the second stage booster of quantum computing: future improvements in the technology will be driven not only by progress in hardware engineering, but also by development of QEC protocols and software that implements them. This software includes high performance parallel decoders that run on powerful classical computers alongside the quantum processor to diagnose errors in real time. I am hiring C++ programmers to build this system. If you enjoy coding close to the OS and hardware, writing highly parallel software, tuning real-time systems, or developing scientific software then consider applying for the position below. Knowledge of quantum computing is not required. https://lnkd.in/gznq9X6D #highperformancecomputing #scientificcomputing #quantumcomputing #softwareengineering