#FeaturedJobFriday: Calling GPU software design experts, this one is for you! We're actively recruiting an experienced engineer who is passionate about GPU performance optimization. You will collaborate with highly skilled hardware and software engineering teams at #WeAreSarcAcl to deliver market-leading GPU performance and efficiency across a range of Samsung IP applications and platforms. Bring your fresh ideas and come build with an organization at the heart of innovation: https://bit.ly/4cScwur
Samsung Semiconductor’s Post
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2 of 25 #job #openings on 3/27 ✴️ #ASIC engineer ✴️ NVIDIA As promised, I am #sharing: ✅ 25 #job #opportunities ✅ 9 #postdoc #positions ✅ 8 #phd #positions ✅ 6 #intern #roles ✅ 5 #faculty #jobs #checkitout, #share and #follow! #opportunity #usajobs #usa #hiring #hiringnow #open #jobsearch #reshare #engineeringjobs #engineering #givingback #spreadtheword #connectandgrow #repost
We’re seeking an ASIC Engineer to join our front-end multi-media IP team to help develop video IPs. You'll be creating micro-arch and implement designs in Verilog and HLS, work with PD and Arch to optimize QOR, and help validate through simulation and emulation/fpga prototypes. One team. Many voices. Infinite possibilities. #NVIDIAlife
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NVIDIAis #hiring several ASIC Timing Engineers to join our headquarters in Santa Clara, California. You will develop and execute timing closure plans for NVIDIA's next generation of #cpu, #gpu and #soc designs and will own STA for large subsystems and full chip designs or at block-level with additional responsibilities for block level synthesis/optimization. You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs to find the right tradeoffs and balance between frequency and power/area/congestions/yield/etc. #asic #asicdesign #rtldesign #rtl #clocking #clock #sta #methodology #methodologies #fullchip #blocklevel #perl #python #santaclara
Senior ASIC Timing Engineer
nvidia.wd5.myworkdayjobs.com
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🚀 Exciting RISC-V Learning Opportunity for Frontend Engineers in VLSI! 🚀 🌐 Dive Deep into Processor Design with RISC-V! 🌐 vlsideepdive is thrilled to share an incredible learning opportunity - a workshop on RISC-V Microarchitecture, RTL Design, and Verification. This program is not just another course; it's a gateway to mastering cutting-edge processor design. 🔍 What's Inside: -> A comprehensive exploration of RISC-V fundamentals. -> Detailed discussions on architectural state, instruction sets, and microarchitecture variations. -> Advanced topics like deep pipelines, branch prediction, superscalar processors, and multithreading. -> Hands-on RTL design using Verilog, with a focus on practical, real-world applications. 🎯 Why This Matters: -> RISC-V is becoming a pivotal architecture in the semiconductor industry. -> Understanding these concepts is crucial for anyone looking to stay ahead in technology and design. -> Whether you're starting or seeking to enhance your skills, this course has something for everyone. Check it out and step into the future of microprocessor design! Contact and Learn more here: https://lnkd.in/gVpirNhG #RISCV #Microarchitecture #TechInnovation #Verilog #ProcessorDesign #FutureOfTech
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🚀 Excited to announce that I'm taking on the 100 Days Verilog Challenge! 💻🔧 For the next 100 days, I'll be diving deep into Verilog, honing my skills in hardware description and digital design. From basic logic gates to complex digital systems, I'm ready to explore and expand my knowledge. Why Verilog? Because it's the language of hardware design, and mastering it opens up a world of opportunities in the semiconductor industry and beyond. Whether it's FPGA programming, ASIC design, or digital signal processing, Verilog is at the heart of it all. I'll be sharing my progress, insights, and challenges along the way, so stay tuned for updates! And if you're also passionate about digital design or Verilog, let's connect and embark on this journey together. Let's code, innovate, and build the future, one Verilog module at a time! 💡💪 #100DaysVerilog #HardwareDesign #DigitalDesign #FPGA #ASIC #Semiconductor #Engineering
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🔧 Unveiling the Power Behind Chips: Most Popular RTL Design Tools in Semiconductor Solutions 🌐💻 Ever wondered what tools engineers use to craft the brains of your favorite gadgets? 🤔 Dive into the world of RTL design in semiconductors with a peek at the most popular tools shaping our tech future! 🔍🚀 1. Vivado by Xilinx: The go-to for FPGA design, Vivado is a powerhouse for RTL synthesis and implementation, pushing the boundaries of innovation. 💡✨ 2. Synopsys Design Compiler: Where performance meets efficiency! This tool is a trailblazer in RTL synthesis, ensuring chips run like a well-oiled machine. ⚙️🚀 3. Cadence Genus: A game-changer in the RTL design realm, Genus is synonymous with speed, optimizing designs for peak performance. 🏎️💨 4. Mentor Graphics Questa: When it comes to functional verification, Questa takes the lead. It's the gatekeeper ensuring chips do exactly what they're supposed to! 🛡️🤖 5. Xilinx Vivado HLS: HLS (High-Level Synthesis) is the future, and Vivado HLS is at the forefront, turning high-level code into efficient hardware. 🔄💻 6. SpyGlass by Synopsys: The Sherlock Holmes of RTL design! SpyGlass uncovers hidden issues, ensuring designs are Sherlock-approved for reliability. 🔍🕵️♂️ Join the conversation! Which RTL design tool do you find most fascinating? 💬✨ #SmartSoC #SemiconductorTech #RTLDesign #TechTools 🚀💻
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Exciting Opportunity Alert! 🚀 Elevate your digital design skills with our upcoming 10-day training program on Basic SystemVerilog and Test Bench Creation. 🎓💻 🚀 Why Attend? Gain a solid foundation in SystemVerilog Learn industry-best practices for test bench development Practical insights for efficient functional verification 🎓 Who Should Attend? Aspiring ASIC/FPGA engineers Verification engineers looking to enhance their skills Anyone keen on mastering SystemVerilog and test bench creation #SystemVerilog #DigitalDesign #Verification #TrainingProgram #CareerDevelopment #ASIC #FPGA #HardwareDesign
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ECE Final year • Gl Bajaj Institute of Technology and Management • Embedded system design • IOT •Cybersecurity
🎓 Excited to share that I've just completed an intensive course in VLSI System - On Chip Design from Maven Silicon! 💻🔌Maven Silicon Throughout this course, I delved deep into the intricacies of on-chip design, mastering concepts like RTL design, synthesis, and verification. 💡 I also gained hands-on experience using industry-standard tools and methodologies, preparing me to tackle real-world VLSI design challenges head-on. 💪 I'm grateful to Maven Silicon for providing such a comprehensive and practical learning experience, and I'm eager to apply my newfound knowledge to future projects in the field of Electrical and Computer Engineering. 🔍🚀 #VLSI #OnChipDesign #MavenSilicon #ElectricalEngineering #ComputerEngineering #rtldesign #verilog
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I am glad to announce that the Maven Silicon Advanced VLSI Design and Verification Course has been completed successfully. Equipped to work on challenges in design in the semiconductor sector with the most advanced abilities. Thankful for the indelible insights and experiences acquired during this significant experience. Learnings and Outcomes: 1.) Digital Electronics 2.) Verilog programming 3.) Static Timing Analysis 4.) System Verilog 5.) Universal Verification Methodology #vlsitraining #vlsijobs #vlsidesign #sta #vlsiverification
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I am' thrilled to share that I've successfully completed the VLSI SoC Design in Verilog HDL certification! 🚀 This comprehensive program covered key aspects of VLSI System-on-Chip (SoC) design, providing in-depth knowledge of Verilog Hardware Description Language (HDL) and its applications in the field. 🔍 Key Learnings: •Understanding SoC architecture •Verilog HDL fundamentals •Designing and implementing complex digital systems •Hand on practice 🤖 Next Steps: Excited to apply my newly acquired skills in real-world projects and contribute to the dynamic field of VLSI design. Open to networking and collaboration opportunities in this space! #VLSI #SoCDesign #VerilogHDL #CertificationAchievement #Semiconductor #Innovation"
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Vellore Institute Of Technology||Electrical and Electronics||Gate aspirant||Power electronics enthusiast||active learner||good listener
Hey connection,recently I have completed a course on Chip design from Maven Silicon and some of the learnings I found in this course are listed below- A11 Chip Insights: Explored the architecture and design principles behind the A11 chip used in iPhones, understanding its circuitry and power management techniques. Verilog Mastery: Gained proficiency in Verilog coding, from basic logic gates to complex SoC architectures, enabling precise digital design and simulation. SoC Architecture Understanding: Delved into System-on-Chip (SoC) architectures, learning to integrate processors, memory, interfaces, and peripherals seamlessly for enhanced performance. IP Integration Skills: Mastered the art of integrating Intellectual Properties (IPs) effectively, selecting, and verifying pre-designed modules to streamline chip development processes. Expressing gratitude for the invaluable guidance and mentorship provided by Maven Silicon, which has been instrumental in shaping expertise and fostering professional growth.😃 #ChipDesign #TechEducation #Engineering #Innovation #DigitalDesign #Hardware #VLSI #Verilog #SoC #IPIntegration #MavenSilicon #CareerGrowth #ProfessionalDevelopment #TechnologyTrends #Networking
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Functional Verification Lead, Senior Member IEEE, IETE Fellow, Functional Safety Expert, Editorial Board Member
1moGreat opportunity!