From the course: Learning Verilog for FPGA Development
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Flip-flops - FPGA Tutorial
From the course: Learning Verilog for FPGA Development
Flip-flops
- Here are some quick details about Flip-Flops I need you to keep in mind. One, Flip-Flops are the building blocks of sequential systems, so if your system has a clock input to keep track of time, it must have Flip-Flops somewhere. Two, Flip-Flops are made of logic gates. Three, they may or may not have a clock input, that is to say, they may be synchronous, or asynchronous. Four, synchronous Flip-Flops may be triggered by the logic level, or state in their clock input, in which case they are referred to as latches. Or they may be triggered by the edges or transitions in the clock line, in which case they are known as registers. And five, there are several types of Flip-Flops which vary in their logic. For example, there are SR, D, JK, and T Flip-Flops. With all this in mind, we may conclude that you may build your sequential circuits from the ground up. For example, here's the schematic of a Master-Slave JK…
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